From dcd6913ec2afa8ec1030bf63df7ca69622cbf4f9 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Pali=20Roh=C3=A1r?= Date: Thu, 10 Mar 2022 21:38:18 +0100 Subject: [PATCH] lspci: Fix detection of memory space bar intel-conf1 backend never show AtomicOpsCap: capabilities despite the fact that is successfuly detects memory bars on device. But other backends show this capability. Error is in device_has_memory_space_bar() function, it expects that ->size member is always filled. But size of the BAR is not available in PCI config space and therefore raw backends cannot retrieve it. Probably intention of the non-zero check was to verify that base address was filled with non-zero size. So either base address is non-zero or length is non-zero. Adjust check. --- ls-caps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ls-caps.c b/ls-caps.c index 3e19cab..a481b16 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -1083,7 +1083,7 @@ device_has_memory_space_bar(struct device *d) int i, found = 0; for (i=0; i<6; i++) - if (p->base_addr[i] && p->size[i]) + if (p->base_addr[i] || p->size[i]) { if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO)) { -- 2.39.2