From d016c32df3d07f180485d7349a0d015deb380ecf Mon Sep 17 00:00:00 2001 From: Nikita Proshkin Date: Wed, 27 Dec 2023 14:44:52 +0500 Subject: [PATCH] lspci: Add Lane Margining support to the lspci Gather all the info available without writing to the config space. Without any commands margining capability exposes only 3 status bits to read through Margining Port Capabilities and Margining Port Status registers. It makes sense to show them anyway. For example, Margining Ready bit indicates whether the device is actually ready for the margining process. Reviewed-by: Sergei Miroshnichenko Signed-off-by: Nikita Proshkin --- ls-ecaps.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/ls-ecaps.c b/ls-ecaps.c index 2d7d827..e73eb14 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -691,6 +691,26 @@ cap_rcec(struct device *d, int where) printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn ); } +static void +cap_lmr(struct device *d, int where) +{ + printf("Lane Margining at the Receiver\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where, 8)) + return; + + u16 port_caps = get_conf_word(d, where + PCI_LMR_CAPS); + u16 port_status = get_conf_word(d, where + PCI_LMR_PORT_STS); + + printf("\t\tPortCap: Uses Driver%c\n", FLAG(port_caps, PCI_LMR_CAPS_DRVR)); + printf("\t\tPortSta: MargReady%c MargSoftReady%c\n", + FLAG(port_status, PCI_LMR_PORT_STS_READY), + FLAG(port_status, PCI_LMR_PORT_STS_SOFT_READY)); +} + static void cxl_range(u64 base, u64 size, int n) { @@ -1607,7 +1627,7 @@ show_ext_caps(struct device *d, int type) printf("Physical Layer 16.0 GT/s \n"); break; case PCI_EXT_CAP_ID_LMR: - printf("Lane Margining at the Receiver \n"); + cap_lmr(d, where); break; case PCI_EXT_CAP_ID_HIER_ID: printf("Hierarchy ID \n"); -- 2.39.5