From a06055803eb60066c2b5a682f4684c32a0578d2a Mon Sep 17 00:00:00 2001 From: Martin Mares Date: Mon, 15 Jul 2019 00:17:29 +0200 Subject: [PATCH] DS18B20: Better timer magic --- lib/ds18b20.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/lib/ds18b20.c b/lib/ds18b20.c index 30ad08e..02a62cf 100644 --- a/lib/ds18b20.c +++ b/lib/ds18b20.c @@ -81,11 +81,9 @@ static bool ds_reset(void) } // Pull line down and start timer - cm_disable_interrupts(); timer_generate_event(DS_TIMER, TIM_EGR_UG); - timer_enable_counter(DS_TIMER); timer_set_oc_mode(DS_TIMER, TIM_OC2, TIM_OCM_INACTIVE); - cm_enable_interrupts(); + timer_enable_counter(DS_TIMER); // Wait until the timer expires while (timer_is_counter_enabled(DS_TIMER)) @@ -114,12 +112,9 @@ static void ds_send_bit(bool bit) timer_set_period(DS_TIMER, 99); // Each write slot takes 100 μs timer_set_oc_mode(DS_TIMER, TIM_OC2, TIM_OCM_FORCE_HIGH); timer_set_oc_value(DS_TIMER, TIM_OC2, (bit ? 3 : 89)); // 1: 3μs pulse, 0: 89μs pulse - cm_disable_interrupts(); - // XXX: On STM32F1, we must configure the OC channel _after_ we enable the counter, - // otherwise OC triggers immediately. Reasons? - timer_enable_counter(DS_TIMER); + timer_generate_event(DS_TIMER, TIM_EGR_UG); timer_set_oc_mode(DS_TIMER, TIM_OC2, TIM_OCM_INACTIVE); - cm_enable_interrupts(); + timer_enable_counter(DS_TIMER); while (timer_is_counter_enabled(DS_TIMER)) ; } @@ -142,10 +137,9 @@ static bool ds_recv_bit(void) dma_set_number_of_data(DS_DMA, DS_DMA_CH, 1); dma_enable_channel(DS_DMA, DS_DMA_CH); timer_set_oc_mode(DS_TIMER, TIM_OC2, TIM_OCM_FORCE_HIGH); - cm_disable_interrupts(); - timer_enable_counter(DS_TIMER); + timer_generate_event(DS_TIMER, TIM_EGR_UG); timer_set_oc_mode(DS_TIMER, TIM_OC2, TIM_OCM_INACTIVE); - cm_enable_interrupts(); + timer_enable_counter(DS_TIMER); while (timer_is_counter_enabled(DS_TIMER)) ; // DEBUG2("XXX %08x\n", ds_dma_buffer); -- 2.39.2