From 942db12faffd599640651f4ac5b8cf881b503a00 Mon Sep 17 00:00:00 2001 From: Martin Mares Date: Sat, 18 Feb 2012 17:57:35 +0100 Subject: [PATCH] Configure: Simplified radix sorter configuration Originally, we guessed based on CPU model, but as I have ripped out model detection, we cannot do that any longer; besides, it was very much out of date. Now, we use simple heuristics: anybody caring about performance runs on amd64 and all amd64 processors have large enough L1 cache to use 12-bit bucket width. --- ucw/perl/UCW/Configure/LibUCW.pm | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/ucw/perl/UCW/Configure/LibUCW.pm b/ucw/perl/UCW/Configure/LibUCW.pm index 46cac732..eda1d259 100644 --- a/ucw/perl/UCW/Configure/LibUCW.pm +++ b/ucw/perl/UCW/Configure/LibUCW.pm @@ -35,13 +35,15 @@ Set("CONFIG_UCW_PARTMAP_IS_MMAP") if IsSet("CPU_64BIT_POINTERS"); Set("CONFIG_UCW_POOL_IS_MMAP"); # Guess optimal bit width of the radix-sorter -if (Get("CPU_ARCH") eq "default" || Get("CPU_ARCH") =~ /^i[345]86$/) { - # This should be safe everywhere - Set("CONFIG_UCW_RADIX_SORTER_BITS" => 10); -} else { - # Use this on modern CPU's - Set("CONFIG_UCW_RADIX_SORTER_BITS" => 12); -} +Test("CONFIG_UCW_RADIX_SORTER_BITS", "Determining radix sorter bucket width", sub { + if (Get("CPU_AMD64")) { + # All amd64 CPUs have large enough L1 cache + return 12; + } else { + # This should be safe everywhere + return 10; + } +}); # Detect if thread-local storage is supported if (Get("CONFIG_UCW_THREADS")) { -- 2.39.2