From 72b9b690e81e539fc6b92958a1544f5379a6fa9f Mon Sep 17 00:00:00 2001 From: Martin Mares Date: Mon, 1 May 2000 21:34:49 +0000 Subject: [PATCH] Updated display of power management information to PCI PM specs 1.1. --- ChangeLog | 2 ++ lib/header.h | 28 ++++++++++++++++------------ lspci.c | 22 ++++++++++++++++------ 3 files changed, 34 insertions(+), 18 deletions(-) diff --git a/ChangeLog b/ChangeLog index 393e132..c67099f 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,7 @@ 2000-05-01 Martin Mares + * lspci.c (show_pm): Updated according to PCI PM specs 1.1. + * pci.ids: Updated Contemporary Control ARCnet card entries. * pci.ids: Synchronized class list with latest PCI SIG documents. diff --git a/lib/header.h b/lib/header.h index 90f4c56..3b7bd78 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1,5 +1,5 @@ /* - * $Id: header.h,v 1.5 2000/01/20 21:15:46 mj Exp $ + * $Id: header.h,v 1.6 2000/05/01 21:34:49 mj Exp $ * * The PCI Library -- PCI Header Structure (extracted from ) * @@ -191,23 +191,27 @@ /* Power Management Registers */ -#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ -#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ -#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ -#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ +#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */ +#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */ +#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization required */ +#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D3cold */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ -#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ +#define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */ +#define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */ +#define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */ +#define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */ +#define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */ #define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ -#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ -#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ +#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */ +#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling factor */ #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ -#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ -#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ -#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ -#define PCI_PM_DATA_REGISTER 7 /* (??) */ +#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */ +#define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */ +#define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */ +#define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */ #define PCI_PM_SIZEOF 8 /* AGP registers */ diff --git a/lspci.c b/lspci.c index b2ce104..eb08436 100644 --- a/lspci.c +++ b/lspci.c @@ -1,5 +1,5 @@ /* - * $Id: lspci.c,v 1.36 2000/04/21 11:58:00 mj Exp $ + * $Id: lspci.c,v 1.37 2000/05/01 21:34:49 mj Exp $ * * Linux PCI Utilities -- List All PCI Devices * @@ -375,26 +375,36 @@ show_bases(struct device *d, int cnt) static void show_pm(struct device *d, int where, int cap) { - int t; + int t, b; + static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 }; printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK); if (verbose < 2) return; - printf("\t\tFlags: PMEClk%c AuxPwr%c DSI%c D1%c D2%c PME%c\n", + printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n", FLAG(cap, PCI_PM_CAP_PME_CLOCK), - FLAG(cap, PCI_PM_CAP_AUX_POWER), FLAG(cap, PCI_PM_CAP_DSI), FLAG(cap, PCI_PM_CAP_D1), FLAG(cap, PCI_PM_CAP_D2), - FLAG(cap, PCI_PM_CAP_PME)); + pm_aux_current[(cap >> 6) & 7], + FLAG(cap, PCI_PM_CAP_PME_D0), + FLAG(cap, PCI_PM_CAP_PME_D1), + FLAG(cap, PCI_PM_CAP_PME_D2), + FLAG(cap, PCI_PM_CAP_PME_D3_HOT), + FLAG(cap, PCI_PM_CAP_PME_D3_COLD)); config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL); t = get_conf_word(d, where + PCI_PM_CTRL); - printf("\t\tStatus: D%d PME-Enable%c DSel=%x DScale=%x PME%c\n", + printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n", t & PCI_PM_CTRL_STATE_MASK, FLAG(t, PCI_PM_CTRL_PME_ENABLE), (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9, (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13, FLAG(t, PCI_PM_CTRL_PME_STATUS)); + b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS); + if (b) + printf("\t\tBridge: PM%c B3%c\n", + FLAG(t, PCI_PM_BPCC_ENABLE), + FLAG(~t, PCI_PM_PPB_B2_B3)); } static void -- 2.39.2