From 60be9345be266524ffa5fd50ac0df4ee12a7b4bd Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Thu, 10 Feb 2022 16:19:45 +0000 Subject: [PATCH] pciutils: Add decode support for Data Object Exchange Extended Capability PCI Data Object Exchange [1] provides a mailbox interface used as the transport for various protocols defined by PCI-SIG and others. Make the limited information in config space available. Note the Read/Write Mailbox registers themselves are not currently parsed as the usefulness of accessing one dword of a protocol is probably limited. In future, operating systems may provide means to safely query the supported protocols, but those have not yet been defined. Example output: Capabilities: [100 v1] Data Object Exchange DOECap: IntSup+ Interrupt Message Number 001 DOECtl: IntEn+ DOESta: Busy- IntSta- Error- ObjectReady+ [1] PCIe r6.0, sections 6.30 and 7.9.24 Signed-off-by: Jonathan Cameron --- lib/header.h | 15 +++ ls-ecaps.c | 38 +++++++ tests/cap-doe | 302 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 355 insertions(+) create mode 100644 tests/cap-doe diff --git a/lib/header.h b/lib/header.h index ec1bb63..a069040 100644 --- a/lib/header.h +++ b/lib/header.h @@ -252,6 +252,7 @@ #define PCI_EXT_CAP_ID_LMR 0x27 /* Lane Margining at Receiver */ #define PCI_EXT_CAP_ID_HIER_ID 0x28 /* Hierarchy ID */ #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ +#define PCI_EXT_CAP_ID_DOE 0x2e /* Data Object Exchange */ /*** Definitions of capabilities ***/ @@ -1255,6 +1256,20 @@ #define PCI_L1PM_SUBSTAT_CTL1_ASPM_L11 0x8 /* ASPM L1.1 Enable */ #define PCI_L1PM_SUBSTAT_CTL2 0xC /* L1 PM Substate Control 2 */ +/* Data Object Exchange Extended Capability */ +#define PCI_DOE_CAP 0x4 /* DOE Capabilities Register */ +#define PCI_DOE_CAP_INT_SUPP 0x1 /* Interrupt Support */ +#define PCI_DOE_CAP_INT_MSG(x) (((x) >> 1) & 0x7ff) /* DOE Interrupt Message Number */ +#define PCI_DOE_CTL 0x8 /* DOE Control Register */ +#define PCI_DOE_CTL_ABORT 0x1 /* DOE Abort */ +#define PCI_DOE_CTL_INT 0x2 /* DOE Interrupt Enable */ +#define PCI_DOE_CTL_GO 0x80000000 /* DOE Go */ +#define PCI_DOE_STS 0xC /* DOE Status Register */ +#define PCI_DOE_STS_BUSY 0x1 /* DOE Busy */ +#define PCI_DOE_STS_INT 0x2 /* DOE Interrupt Status */ +#define PCI_DOE_STS_ERROR 0x3 /* DOE Error */ +#define PCI_DOE_STS_OBJECT_READY 0x80000000 /* Data Object Ready */ + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded diff --git a/ls-ecaps.c b/ls-ecaps.c index 2c0264e..15c57a8 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -992,6 +992,41 @@ cap_rebar(struct device *d, int where, int virtual) } } +static void +cap_doe(struct device *d, int where) +{ + u32 l; + + printf("Data Object Exchange\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_DOE_CAP, 0x14)) + { + printf("\t\t\n"); + return; + } + + l = get_conf_long(d, where + PCI_DOE_CAP); + printf("\t\tDOECap: IntSup%c\n", + FLAG(l, PCI_DOE_CAP_INT_SUPP)); + if (l & PCI_DOE_CAP_INT_SUPP) + printf("\t\t\tInterrupt Message Number %03x\n", + PCI_DOE_CAP_INT_MSG(l)); + + l = get_conf_long(d, where + PCI_DOE_CTL); + printf("\t\tDOECtl: IntEn%c\n", + FLAG(l, PCI_DOE_CTL_INT)); + + l = get_conf_long(d, where + PCI_DOE_STS); + printf("\t\tDOESta: Busy%c IntSta%c Error%c ObjectReady%c\n", + FLAG(l, PCI_DOE_STS_BUSY), + FLAG(l, PCI_DOE_STS_INT), + FLAG(l, PCI_DOE_STS_ERROR), + FLAG(l, PCI_DOE_STS_OBJECT_READY)); +} + void show_ext_caps(struct device *d, int type) { @@ -1139,6 +1174,9 @@ show_ext_caps(struct device *d, int type) case PCI_EXT_CAP_ID_NPEM: printf("Native PCIe Enclosure Management \n"); break; + case PCI_EXT_CAP_ID_DOE: + cap_doe(d, where); + break; default: printf("Extended Capability ID %#02x\n", id); break; diff --git a/tests/cap-doe b/tests/cap-doe new file mode 100644 index 0000000..562f1cb --- /dev/null +++ b/tests/cap-doe @@ -0,0 +1,302 @@ +df:00.0 Class 0502: Device 8086:0d93 (rev 01) (prog-if 10) + Subsystem: Device 1af4:1100 + Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR-