Pali Rohár [Thu, 18 May 2023 19:36:50 +0000 (21:36 +0200)]
libpci: ecam: Fix big address range mappings
If more buses span continuous address space then there can be up to the
256 MB long address range which ecam backend tries to map.
Such huge space cannot be mapped on some memory limited systems. And also
it is not needed to map whole 256 MB long address range because ecam
backend cache uses mapping only for one bus. One bus has maximal mapping
size just 32*8*4096 bytes.
Pali Rohár [Thu, 17 Aug 2023 20:03:19 +0000 (22:03 +0200)]
libpci: win32-cfgmgr32: Do not use GetWindowsDirectory()
GetWindowsDirectory() function returns HOME user folder if application is
running on the Terminal Server. So this function is not suitable.
Instead of use GetSystemDirectory() which returns path to system32 folder
or GetSystemWindowsDirectory() which returns path to Windows folder (but
this is not available on all Windows versions).
Pali Rohár [Thu, 17 Aug 2023 19:15:02 +0000 (21:15 +0200)]
libpci: win32-kldbg: Fix driver constructing path
Get*Directory() functions have strange API. When called with zero buffer
they return length of the required buffer for storing path including
nul-term in TCHAR units (which is 1 for ANSI builds and 2 for UNICODE
builds). When called with non-zero buffer which can store full path they
return length of the path without nul-term (again in TCHAR units).
GetWindowsDirectory() function returns HOME user folder if application is
running on the Terminal Server. So this function is not suitable.
Fix calculation of path buffer for UNICODE builds and instead of usage
GetWindowsDirectory() function with concatenating "\\system32" string, use
function GetSystemDirectory() which returns path directly to system32
folder and which works correctly also on Terminal Server (per KB281316).
Ilpo Järvinen [Fri, 8 Dec 2023 10:13:07 +0000 (12:13 +0200)]
lspci: Add PCIe 6.0 data rate (64 GT/s) also to LnkCap2
While commit 5bdf63b6b1bc ("lspci: Add PCIe 6.0 data rate (64 GT/s)
support") added 64 GT/s support to some registers, LnkCap2 Supported
Link Speeds Vector was not included.
Add PCIe 6.0 data rate bit check also into
cap_express_link2_speed_cap().
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Ashok Raj [Wed, 18 Oct 2023 21:34:15 +0000 (14:34 -0700)]
Subject: lspci: Display PASID required attribute in Page Status Register.
Display the PASID required attribute in the Page Request Status Register.
When set, the function expects a PASID on Page Group Response (PRG)
messages when the corresponding page request had a PASID.
Decode the PCIe DevCtl2 End-to-End TLP Prefix Blocking bit. The
"EETLPPrefixBlk" format is analogous to the existing "EETLPPrefix" format
used for the corresponding DevCap2 bit.
Martin Mares [Sat, 22 Jul 2023 21:47:13 +0000 (23:47 +0200)]
update-pciids: Re-compress pci.ids if needed
Previously, if pciutils were configured with compression of pci.ids,
update-pciids downloaded the gzipped version. Now, it downloads the
most compressed version for which tools are found installed, and
recompresses it to gzip if needed.
David Edmondson [Wed, 19 Jul 2023 14:16:41 +0000 (15:16 +0100)]
lspci: Use mangled vendor/device ID when examining vendor caps
Given that PCI VFs are expected to have a vendor and device ID of
0xffff, when examining vendor capabilities use the mangled vendor and
device IDs (typically copied from the PF) rather than those read from
the VF configuration space.
Signed-off-by: David Edmondson <david.edmondson@oracle.com>
The error bit is specified by the 2nd (zero indexed) bit
in the status register, so the respective bit value is 4 (PCI Base Spec
6.0.1). Let's fix that up.
ls-tree: Fix parsing devices on multidomain PCI system
Represent each domain as domain bridge under the &host_bridge and put root
bus of each domain under the domain bridge.
With this change lspci in tree view does not show zero bus on domain 0 in
the output if this bus does not exist at all. Root bus in PCIe hierarchy
does not have to be zero and on Freescale PowerPC systems it is common.
Also with this change are separate domain showed in the output separately.
ls-tree: Do not read Primary Bus Number for PCI Bridges from PCI config space
For PCIe devices of PCI Bridge type is Primary Bus Number not used and the
default value is 0. PCIe devices capture their Bus and Device numbers
automatically from PCIe TLP packets.
Instead of Primary Bus Number use Device Number because zero value confuse
tree building algorithm. Existing code already expects that Device Number
of PCI Bridge is already set to Primary Bus Number.
Martin Mares [Sun, 5 Mar 2023 13:56:52 +0000 (14:56 +0100)]
Parameters: Keep the list sorted and remove duplicates
When multiple back-ends use the same option (e.g., "devmem.path"),
they tend to define it each. This is not nice, but before we generalize
these options properly, let us at least remove the duplicate definitions.
Pali Rohár [Sun, 29 Jan 2023 23:39:36 +0000 (00:39 +0100)]
libpci: Add PCIe ECAM access method
This is a new direct hardware access method via PCIe ECAM (Enhanced
Configuration Access Mechanism). It is available on all PCIe-compliant
hardware. Requires root privileges and access to physical memory.
ECAM mapping can be specified manually via a new ecam.addrs parameter or
can be read from ACPI MCFG table. ACPI MCFG table can be located in the
system or read from x86 BIOS memory.
Martin Mares [Sat, 4 Mar 2023 15:33:09 +0000 (16:33 +0100)]
Use "command -v" instead of "which"
Apparently, people started considering "which" obsolete. I still
consider "which" rather useful and definitely more comfortable to type
than "command -v".
Still, "command -v" should be more portable, so let us use it.
I wonder which of the ancient systems which we are still supporting
will be broken by this change...
Pali Rohár [Sun, 29 Jan 2023 22:49:06 +0000 (23:49 +0100)]
libpci: mmio-ports: Fix support for 64-bit non-LLP64 systems
On 64-bit non-LLP64 systems is type long 64-bit. On 32-bit and 64-bit LLP64
systems is type long only 32-bit. But readl() and writel() functions works
with 32-bit PCI word. Fix it for non-LLP64 systems by using type u32.
Pali Rohár [Fri, 30 Dec 2022 20:21:10 +0000 (21:21 +0100)]
libpci: win32-cfgmgr32: Add support for accessing config space via other backend
Extend win32-cfgmgr32 backend and add a new option win32.cfgmethod for
specifying other backend for accessing PCI config space. There are more
config space access methods available on Windows and each is working only
sometimes (either requires special privileges or special setup).
So by default try to choose the first working one via order defined in pci
probe_sequence[] array. If none is available then emulate PCI config space
like before this change.
Function pci_init_v35() is extended and renamed to pci_init_internal() to
optionally do not throw errors and allow to specify one access method which
will be skipped in AUTO mode. This is used to prevent choosing win32-cfgmgr32
as config space access method for win32-cfgmgr32.
Pali Rohár [Fri, 18 Nov 2022 22:40:39 +0000 (23:40 +0100)]
libpci: windows: Handle long paths generated by GetModuleFileName()
C function fopen() implemented by msvcrt.dll requires special prefix
"\\\\?\\" for paths longer than 260 bytes. Because GetModuleFileName()
returns absolute path, it may be longer than 260 bytes. Add fixup to handle
long paths.
Pali Rohár [Fri, 18 Nov 2022 20:57:50 +0000 (21:57 +0100)]
libpci: djgpp: Allow to specify empty IDSDIR=
Like for windows builds this will cause to load pci.ids file from the same
directory where is stored application binary. Code is same as for Windows,
just djgpp uses global symbol __dos_argv0 instead of _pgmptr.
Tested with following compile command:
make CROSS_COMPILE=i586-pc-msdosdjgpp- HOST=i586-djgpp ZLIB=no DNS=no IDSDIR=
Pali Rohár [Fri, 18 Nov 2022 20:54:53 +0000 (21:54 +0100)]
libpci: windows: Fix locating path to pci.ids file for DLL builds
When using shared libpci DLL library, it is expected that pci.ids file is
stored in directory where is also libpci DLL library and not in directory
where is application executable.
Based on the build mode and compile options, choose the appropriate
function for retrieving path to the libpci DLL library or application
executable. Also pass correct module argument to GetModuleFileName() call.
Pali Rohár [Fri, 18 Nov 2022 20:47:04 +0000 (21:47 +0100)]
libpci: windows: Fix usage of GetModuleFileName()
Module file name can have arbitrary length despite all MS examples say
about MAX_PATH upper limit. This limit does not apply for example when
executable is running from network disk with very long UNC paths or
when using "\\??\\" prefix for specifying executable binary path.
So handle buffer truncatenation by retrying GetModuleFileName() call with
larger buffer.
Fixes loading of pci.ids file when lspci.exe binary is running from network
drive with path longer than 260 bytes.
Pali Rohár [Sun, 2 Jan 2022 19:50:41 +0000 (20:50 +0100)]
libpci: mmio-ports: Add Extended PCIe Intel Type 1 access method
Extended method allows to access all PCIe registers, including extended
registers starting at 0x100 offset. This method uses 4 reserved buts above
bus bits for PCIe registers. On ARM platforms it is very common for PCIe
controllers. Like standard method, it needs to be properly configured.
Pali Rohár [Fri, 4 Mar 2022 00:07:53 +0000 (01:07 +0100)]
libpci: Add new windows kldbgdrv.sys implementation
Microsoft Kernel Local Debugging Driver (kldbgdrv.sys) allow access for
userspace processes to the PCI config space. It supports access up to
65536 domains and whole 4096 bytes long extended PCIe config space. Driver
is signed by Microsoft and is available for both 32-bit and 64-bit systems.
Driver is not part of Windows system and has to be installed via WinDbg
installation package. Standalone installers for WinDbg 6.12.2.633 version:
https://download.microsoft.com/download/A/6/A/A6AC035D-DA3F-4F0C-ADA4-37C8E5D34E3D/setup/WinSDKDebuggingTools_amd64/dbg_amd64.msi
https://download.microsoft.com/download/A/6/A/A6AC035D-DA3F-4F0C-ADA4-37C8E5D34E3D/setup/WinSDKDebuggingTools/dbg_x86.msi
This kldbgdrv.sys API is used by the !pci command of new WinDbg kernel
debugger for displaying PCI config space.
API of this driver is available only for processes with Debug privilege and
only if system was booted with Debugging option.
Pali Rohár [Sun, 6 Nov 2022 17:57:39 +0000 (18:57 +0100)]
i386-ports: Fix intel_io_lock usage
Do not call pci_generic_block_read() and pci_generic_block_write()
functions when io is locked. These functions call back same backend
read/write function which tries to lock and unlock io again.
Pali Rohár [Sun, 6 Nov 2022 12:58:55 +0000 (13:58 +0100)]
i386-io-linux: Prefer usage of ioperm()
Since Linux 2.6.8, it is possible to use ioperm() syscall to gain access
for all I/O ports. Because iopl() syscall before Linux 5.5 allowed
userspace to disable interrupts, prefer usage of ioperm() syscall and ask
for access only for PCI ports.
Pali Rohár [Sun, 2 Jan 2022 19:50:41 +0000 (20:50 +0100)]
libpci: Add Intel Type 1 implementation for memory mapped systems
Lot of non-x86 platforms also support Intel Type 1 mechanism. x86 IO ports
CF8 and CFC are on these platforms mapped into standard memory space.
Address mapping itself is platform or board specific and there is no
default value.
Lot of ARM boards with multiple PCIe controllers are multi-domain and each
PCI domain has its own CF8/CFC (address/data) registers mapped into memory
space.
Add new mmio-conf1 backend which access CF8/CFC ports via MMIO and define
new config option mmio-conf1.addrs which specify list of address/data
register pairs in memory space for each PCI domain. Format of this option
is: 0xaddr1/0xdata1,0xaddr2/0xdata2,...