From: Alex Martens Date: Sun, 25 Jan 2026 18:40:34 +0000 (-0800) Subject: lspci: add test with capabilities 32, 34, and 36 X-Git-Url: http://mj.ucw.cz/gitweb/?a=commitdiff_plain;h=d5b95c5e4e2f8f11d2f721a3f790c580ab94f9a3;p=pciutils.git lspci: add test with capabilities 32, 34, and 36 - h0032: Flit logging - h0034: Flit error injection - h0036: MMIO register block locator --- diff --git a/tests/cap-flit-log b/tests/cap-flit-log new file mode 100644 index 0000000..d1811c9 --- /dev/null +++ b/tests/cap-flit-log @@ -0,0 +1,356 @@ +01:00.0 Class 0604: Device 1234:1b36 (rev 01) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [70] Express (v2) Upstream Port, IntMsgNum 0 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 0W TEE-IO- + DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+ + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend- + LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s <64ns + ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- + LnkCtl: ASPM Disabled; LnkDisable- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- FltModeDis- + LnkSta: Speed 2.5GT/s, Width x1 + TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- + DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR- + 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 4 + EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- + FRS- + AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS- + DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- + AtomicOpsCtl: EgressBlck- + IDOReq- IDOCompl- LTR- EmergencyPowerReductionReq- + 10BitTagReq- OBFF Disabled, EETLPPrefixBlk- + LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis- + Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- + Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot + LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete- EqualizationPhase1- + EqualizationPhase2- EqualizationPhase3- LinkEqualizationRequest- + Retimer- 2Retimers- CrosslinkRes: unsupported, FltMode- + Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ + Address: 0000000000000000 Data: 0000 + Capabilities: [100 v2] Advanced Error Reporting + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- + ECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr- + PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- + UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- + ECRC- UnsupReq- ACSViol- UncorrIntErr+ BlockedTLP- AtomicOpBlocked- TLPBlockedErr+ + PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- + UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ + ECRC- UnsupReq- ACSViol- UncorrIntErr+ BlockedTLP- AtomicOpBlocked- TLPBlockedErr- + PoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked- + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- CorrIntErr- HeaderOF- + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ CorrIntErr+ HeaderOF+ + AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn- + MultHdrRecCap+ MultHdrRecEn- TLPPfxPres- HdrLogCap- + HeaderLog: 00000000 00000000 00000000 00000000 + Capabilities: [500 v1] MMIO Register Block Locator + Locator0: BIR: BAR0, ID: MCAP, offset: 0000000000010000 + Capabilities: [458 v1] Flit Logging + Log1: Valid-, Link Width: x1 + More entries- Unrecognized flit- FEC uncorrectable- + SyndParityGrp0: 00, SyndCheckGrp0: 00 + Log2: SyndParityGrp1: 00, SyndCheckGrp1: 00 + SyndParityGrp2: 00, SyndCheckGrp2: 00 + CntCtl: Flit Error Counter En- Flit Error Counter Interrupt En- + Events to count: 0, Trigger Event on Error Count: 00 + CntSts: Link Width when Error Counter Started x1 + Interrupt Generated based on Trigger Event Count-, FlitErr: 0 + MeasCtl: En- Granularity: all + MeasSts1: Flit Counter: 0 + MeasSts2: Invalid Flit Counter: 0 + MeasSts3: Lane0: 0, Lane1: 0 + MeasSts4: Lane2: 0, Lane3: 0 + MeasSts5: Lane4: 0, Lane5: 0 + MeasSts6: Lane6: 0, Lane7: 0 + MeasSts7: Lane8: 0, Lane9: 0 + MeasSts8: Lane10: 0, Lane11: 0 + MeasSts9: Lane12: 0, Lane13: 0 + MeasSts10: Lane14: 0, Lane15: 0 + Capabilities: [4a8 v1] Flit Error Injection + FlitEiCtl1: En- Tx- Rx- 2.5GT/s- 5.0GT/s- 8.0GT/s- 16.0GT/s- 32.0GT/s- 64.0GT/s- + Number of errors: 0, Spacing between errors: 0, Flit Type: any + FlitEiCtl2: Consecutive: none, Type: random, Offset: 0, Magnitude: 0 + FlitEiSts: Tx: not started, Rx: not started + FlitEiOsCtl1: En- Tx- Rx- TS0- TS1- TS2- SKP- EIEOS- EIOS- + SDS- Poll- Conf- L0- NoEq- Eq01- Eq2- Eq3- + FlitEiOsCtl2: Bytes: 0000, Lanes: 0000 + FlitEiOsTx: TS0: not started, TS1: not started, TS2: not started + SKP: not started, EIEOS: not started, EIOS: not started + SDS: not started, Polling: not started, Configuration: not started + L0: not started, non-EQ recovery: not started, Eq01: not started + Eq2: not started, Eq3: not started + FlitEiOsRx: TS0: not started, TS1: not started, TS2: not started + SKP: not started, EIEOS: not started, EIOS: not started + SDS: not started, Polling: not started, Configuration: not started + L0: not started, non-EQ recovery: not started, Eq01: not started + Eq2: not started, Eq3: not started +00: 34 12 36 1b 07 00 10 00 01 00 04 06 00 00 01 00 +10: 04 00 60 81 00 00 00 00 01 02 05 00 10 30 00 00 +20: 00 81 50 81 11 00 91 00 08 00 00 00 08 00 00 00 +30: 00 00 00 00 70 00 00 00 00 00 00 00 ff 00 02 00 +40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +50: 05 00 80 00 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