From: Nikita Proshkin <n.proshkin@yadro.com>
Date: Wed, 22 May 2024 16:06:33 +0000 (+0300)
Subject: pcilmr: Apply grading quirk for Ice Lake RC ports
X-Git-Tag: v3.13.0~9
X-Git-Url: http://mj.ucw.cz/gitweb/?a=commitdiff_plain;h=6de412a1f06de4d4e180c97a2e7dc393de072e33;p=pciutils.git

pcilmr: Apply grading quirk for Ice Lake RC ports

Ice Lake RC ports don't support two side independent timing margining,
however the entire margin across the eye is what is reported by one side
margining. Utility already has quirks for Ice Lake RC, so expand them
based on this grading information.

Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
---

diff --git a/lmr/margin.c b/lmr/margin.c
index 6ce4fe6..d05bb59 100644
--- a/lmr/margin.c
+++ b/lmr/margin.c
@@ -143,13 +143,17 @@ margin_report_cmd(struct margin_dev *dev, u8 lane, margin_cmd cmd, margin_cmd *r
 }
 
 static void
-margin_apply_hw_quirks(struct margin_recv *recv)
+margin_apply_hw_quirks(struct margin_recv *recv, struct margin_link_args *args)
 {
   switch (recv->dev->hw)
     {
       case MARGIN_ICE_LAKE_RC:
         if (recv->recvn == 1)
-          recv->params->volt_offset = 12;
+          {
+            recv->params->volt_offset = 12;
+            args->recv_args[recv->recvn - 1].t.one_side_is_whole = true;
+            args->recv_args[recv->recvn - 1].t.valid = true;
+          }
         break;
       default:
         break;
@@ -341,7 +345,7 @@ margin_test_receiver(struct margin_dev *dev, u8 recvn, struct margin_link_args *
 
   if (recv.parallel_lanes > params.max_lanes + 1)
     recv.parallel_lanes = params.max_lanes + 1;
-  margin_apply_hw_quirks(&recv);
+  margin_apply_hw_quirks(&recv, args);
   margin_log_hw_quirks(&recv);
 
   results->tim_off_reported = params.timing_offset != 0;
diff --git a/lmr/margin_log.c b/lmr/margin_log.c
index 88e3594..60c135d 100644
--- a/lmr/margin_log.c
+++ b/lmr/margin_log.c
@@ -162,7 +162,8 @@ margin_log_hw_quirks(struct margin_recv *recv)
         if (recv->recvn == 1)
           margin_log("\nRx(A) is Intel Ice Lake RC port.\n"
                      "Applying next quirks for margining process:\n"
-                     "  - Set MaxVoltageOffset to 12 (120 mV).\n");
+                     "  - Set MaxVoltageOffset to 12 (120 mV);\n"
+                     "  - Force the use of 'one side is the whole' grading mode.\n");
         break;
       default:
         break;