From: Martin Mares Date: Sun, 24 Mar 2002 12:58:05 +0000 (+0000) Subject: Added PCI-X stuff. X-Git-Tag: v3.0.0~200 X-Git-Url: http://mj.ucw.cz/gitweb/?a=commitdiff_plain;h=5f5e6f64ca0fa1ec2d49b129e3c05ba36223e2e1;p=pciutils.git Added PCI-X stuff. --- diff --git a/ChangeLog b/ChangeLog index d74e08a..4765457 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,12 @@ 2002-03-24 Martin Mares + * lspci.c (show_pcix_bridge): Added PCI-X capability display. + Contributed by Jeff Garzik . + + * lib/header.h: Added PCI-X stuff. Again by Jeff. + + * Makefile (CFLAGS): -Werror is gone. + * lspci.c (format_agp_rate): Fixed AGP rate reporting. * lib/filter.c (pci_filter_parse_slot): Allow bus 0xff, slot 0x1f and diff --git a/lib/header.h b/lib/header.h index 3b7bd78..c92281d 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1,5 +1,5 @@ /* - * $Id: header.h,v 1.6 2000/05/01 21:34:49 mj Exp $ + * $Id: header.h,v 1.7 2002/03/24 12:58:05 mj Exp $ * * The PCI Library -- PCI Header Structure (extracted from ) * @@ -185,6 +185,7 @@ #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ +#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ #define PCI_CAP_SIZEOF 4 @@ -257,6 +258,56 @@ #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ +/* PCI-X */ +#define PCI_PCIX_COMMAND 2 /* Command register offset */ +#define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */ +#define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */ +#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070 +#define PCI_PCIX_COMMAND_RESERVED 0xf80 +#define PCI_PCIX_STATUS 4 /* Status register offset */ +#define PCI_PCIX_STATUS_FUNCTION 0x00000007 +#define PCI_PCIX_STATUS_DEVICE 0x000000f8 +#define PCI_PCIX_STATUS_BUS 0x0000ff00 +#define PCI_PCIX_STATUS_64BIT 0x00010000 +#define PCI_PCIX_STATUS_133MHZ 0x00020000 +#define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ +#define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ +#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */ +#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */ +#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000 +#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000 +#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */ +#define PCI_PCIX_STATUS_RESERVED 0xc0000000 +#define PCI_PCIX_SIZEOF 4 + +/* PCI-X Bridges */ +#define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001 +#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002 +#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020 +#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0 +#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00 +#define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */ +#define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007 +#define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8 +#define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00 +#define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000 +#define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000 +#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ +#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ +#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */ +#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000 +#define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000 +#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */ +#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */ +#define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff +#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000 +#define PCI_PCIX_BRIDGE_SIZEOF 12 + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded diff --git a/lspci.c b/lspci.c index 6b9b982..a6ac32c 100644 --- a/lspci.c +++ b/lspci.c @@ -1,5 +1,5 @@ /* - * $Id: lspci.c,v 1.39 2002/03/24 12:24:34 mj Exp $ + * $Id: lspci.c,v 1.40 2002/03/24 12:58:05 mj Exp $ * * Linux PCI Utilities -- List All PCI Devices * @@ -457,6 +457,86 @@ show_agp(struct device *d, int where, int cap) rate); } +static void +show_pcix_nobridge(struct device *d, int where) +{ + u16 command = get_conf_word(d, where + PCI_PCIX_COMMAND); + u32 status = get_conf_long(d, where + PCI_PCIX_STATUS); + printf("PCI-X non-bridge device.\n"); + if (verbose < 2) + return; + printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n", + FLAG(command, PCI_PCIX_COMMAND_DPERE), + FLAG(command, PCI_PCIX_COMMAND_ERO), + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U), + ((command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U)); + printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, DC=%s, DMMRBC=%u, DMOST=%u, DMCRS=%u, RSCEM%c", + ((status >> 8) & 0xffU), // bus + ((status >> 3) & 0x1fU), // dev + (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function + FLAG(status, PCI_PCIX_STATUS_64BIT), + FLAG(status, PCI_PCIX_STATUS_133MHZ), + FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED), + FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC), + ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"), + ((status >> 21) & 3U), + ((status >> 23) & 7U), + ((status >> 26) & 7U), + FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS)); +} + +static void +show_pcix_bridge(struct device *d, int where) +{ + u16 secstatus; + u32 status, upstcr, downstcr; + printf("PCI-X bridge device.\n"); + if (verbose < 2) + return; + secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS); + printf("\t\tSecondary Status: 64bit%c, 133MHz%c, SCD%c, USC%c, SCO%c, SRD%c Freq=%d\n", + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT), + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ), + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED), + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC), + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN), + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED), + ((secstatus >> 6) & 7)); + status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS); + printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, SCO%c, SRD%c\n", + ((status >> 8) & 0xff), // bus + ((status >> 3) & 0x1f), // dev + (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function + FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT), + FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ), + FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED), + FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC), + FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN), + FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED)); + upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL); + printf("\t\t: Upstream: Capacity=%u, Commitment Limit=%u\n", + (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY), + (upstcr >> 16) & 0xffff); + downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL); + printf("\t\t: Downstream: Capacity=%u, Commitment Limit=%u\n", + (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY), + (downstcr >> 16) & 0xffff); +} + +static void +show_pcix(struct device *d, int where) +{ + switch (d->dev->hdrtype) + { + case PCI_HEADER_TYPE_NORMAL: + show_pcix_nobridge(d, where); + break; + case PCI_HEADER_TYPE_BRIDGE: + show_pcix_bridge(d, where); + break; + } +} + static void show_rom(struct device *d) { @@ -559,6 +639,9 @@ show_caps(struct device *d) case PCI_CAP_ID_MSI: show_msi(d, where, cap); break; + case PCI_CAP_ID_PCIX: + show_pcix(d, where); + break; default: printf("#%02x [%04x]\n", id, cap); }