From: Frederick Lawler Date: Fri, 22 Feb 2019 05:13:26 +0000 (-0600) Subject: lspci: Decode all defined fields in the Device Capabilities 2 register X-Git-Tag: v3.6.3~19 X-Git-Url: http://mj.ucw.cz/gitweb/?a=commitdiff_plain;h=33226851677b92fffd186002d74a1a515fb49413;p=pciutils.git lspci: Decode all defined fields in the Device Capabilities 2 register Decode all defined fields in the Device Capabilities 2 register. The difference from "lspci -vv" output now looks like this: - DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+ + DevCap2: Completion Timeout: Range ABC, TimeoutDis+, NROPrPrP-, LTR+ + 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix- + EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- + FRS-, LN System CLS Not Supported, TPHComp-, ExtTPHComp-, ARIFwd+ Signed-off-by: Frederick Lawler --- diff --git a/lib/header.h b/lib/header.h index ddc1e94..bfdcc80 100644 --- a/lib/header.h +++ b/lib/header.h @@ -873,8 +873,19 @@ #define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */ #define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */ #define PCI_EXP_DEVCAP2 0x24 /* Device capabilities 2 */ +#define PCI_EXP_DEVCAP2_NROPRPRP 0x0400 /* No RO-enabled PR-PR Passing */ #define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */ +#define PCI_EXP_DEVCAP2_TPH_COMP(x) (((x) >> 12) & 3) /* TPH Completer Supported */ +#define PCI_EXP_DEVCAP2_LN_CLS(x) (((x) >> 14) & 3) /* LN System CLS Supported */ +#define PCI_EXP_DEVCAP2_10BIT_TAG_COMP 0x00010000 /* 10 Bit Tag Completer */ +#define PCI_EXP_DEVCAP2_10BIT_TAG_REQ 0x00020000 /* 10 Bit Tag Requester */ #define PCI_EXP_DEVCAP2_OBFF(x) (((x) >> 18) & 3) /* OBFF supported */ +#define PCI_EXP_DEVCAP2_EXTFMT 0x00100000 /* Extended Fmt Field Supported */ +#define PCI_EXP_DEVCAP2_EE_TLP 0x00200000 /* End-End TLP Prefix Supported */ +#define PCI_EXP_DEVCAP2_MEE_TLP(x) (((x) >> 22) & 3) /* Max End-End TLP Prefixes */ +#define PCI_EXP_DEVCAP2_EPR(x) (((x) >> 24) & 3) /* Emergency Power Reduction Supported */ +#define PCI_EXP_DEVCAP2_EPR_INIT 0x04000000 /* Emergency Power Reduction Initialization Required */ +#define PCI_EXP_DEVCAP2_FRS 0x80000000 /* FRS supported */ #define PCI_EXP_DEVCTL2 0x28 /* Device Control */ #define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */ #define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */ diff --git a/ls-caps.c b/ls-caps.c index a739f46..88964ce 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -985,6 +985,52 @@ static const char *cap_express_devcap2_obff(int obff) } } +static const char *cap_express_devcap2_epr(int epr) +{ + switch (epr) + { + case 1: + return "Dev Specific"; + case 2: + return "Form Factor Dev Specific"; + case 3: + return "Reserved"; + default: + return "Not Supported"; + } +} + +static const char *cap_express_devcap2_lncls(int lncls) +{ + switch (lncls) + { + case 1: + return "64byte cachelines"; + case 2: + return "128byte cachelines"; + case 3: + return "Reserved"; + default: + return "Not Supported"; + } +} + +static const char *cap_express_devcap2_tphcomp(int tph) +{ + switch (tph) + { + case 1: + return "TPHComp+, ExtTPHComp-"; + case 2: + /* Reserved; intentionally left blank */ + return ""; + case 3: + return "TPHComp+, ExtTPHComp+"; + default: + return "TPHComp-, ExtTPHComp-"; + } +} + static const char *cap_express_devctl2_obff(int obff) { switch (obff) @@ -1027,13 +1073,38 @@ static void cap_express_dev2(struct device *d, int where, int type) int has_mem_bar = device_has_memory_space_bar(d); l = get_conf_long(d, where + PCI_EXP_DEVCAP2); - printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s", - cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)), - FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS), - FLAG(l, PCI_EXP_DEVCAP2_LTR), - cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l))); + printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, NROPrPrP%c, LTR%c", + cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)), + FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS), + FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP), + FLAG(l, PCI_EXP_DEVCAP2_LTR)); + printf("\n\t\t\t 10BitTagComp%c, 10BitTagReq%c, OBFF %s, ExtFmt%c, EETLPPrefix%c", + FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP), + FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ), + cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)), + FLAG(l, PCI_EXP_DEVCAP2_EXTFMT), + FLAG(l, PCI_EXP_DEVCAP2_EE_TLP)); + + if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP)) + { + printf(", MaxEETLPPrefixes %d", + PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4); + } + + printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c", + cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)), + FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT)); + printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS)); + + if (type == PCI_EXP_TYPE_ROOT_PORT) + printf(", LN System CLS %s", + cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l))); + + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT) + printf(", %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l))); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM) - printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI)); + printf(", ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI)); else printf("\n"); if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || diff --git a/tests/cap-exp-dev2 b/tests/cap-exp-dev2 index 9b3bc9a..5b4a56c 100644 --- a/tests/cap-exp-dev2 +++ b/tests/cap-exp-dev2 @@ -1,4 +1,4 @@ -00:1c.0 PCI bridge: Intel Corporation Device 9d10 (rev f1) (prog-if 00 [Normal decode]) +00:1c.0 Class 0604: Device 8086:9d10 (rev f1) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + BridgeCtl: Parity- SERR- NoISA- VGA- VGA16- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0 ExtTag- RBE+ - DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 256 bytes, MaxReadReq 128 bytes - DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- - LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L0s <1us, L1 <16us + DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- + LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L1 <16us ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- - LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- + LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) + TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #0, PowerLimit 10.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- @@ -31,7 +32,10 @@ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- - DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+ + DevCap2: Completion Timeout: Range ABC, TimeoutDis+, NROPrPrP-, LTR+ + 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix- + EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- + FRS-, LN System CLS Not Supported, TPHComp-, ExtTPHComp-, ARIFwd+ AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- AtomicOpsCtl: ReqEn- EgressBlck- @@ -42,7 +46,7 @@ EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 - Capabilities: [90] Subsystem: Lenovo Device 2238 + Capabilities: [90] Subsystem: Device 17aa:2238 Capabilities: [a0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- @@ -50,8 +54,8 @@ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt+ RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- - CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- - CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- HeaderLog: 00000000 00000000 00000000 00000000 @@ -68,7 +72,9 @@ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ T_CommonMode=60us LTR1.2_Threshold=163840ns L1SubCtl2: T_PwrOn=60us - Capabilities: [220 v1] #19 + Capabilities: [220 v1] Secondary PCI Express + LnkCtl3: LnkEquIntrruptEn-, PerformEqu- + LaneErrStat: 0 00: 86 80 10 9d 07 00 10 00 f1 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 f0 00 00 20 20: 10 f1 10 f1 f1 ff 01 00 00 00 00 00 00 00 00 00