From: Bjorn Helgaas Date: Mon, 8 Dec 2008 21:11:19 +0000 (-0700) Subject: lspci: fix "suprise" typo X-Git-Tag: v3.1-alpha3~3 X-Git-Url: http://mj.ucw.cz/gitweb/?a=commitdiff_plain;h=1d03d3414810f1d1f114e037a0f9b4ba2c993dea;p=pciutils.git lspci: fix "suprise" typo This patch corrects the spelling of "surprise." Signed-off-by: Bjorn Helgaas --- diff --git a/ls-caps.c b/ls-caps.c index 0a19d47..8b0f820 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -752,7 +752,7 @@ static void cap_express_link(struct device *d, int where, int type) aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10), latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12), latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15)); - printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n", + printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c\n", FLAG(t, PCI_EXP_LNKCAP_CLOCKPM), FLAG(t, PCI_EXP_LNKCAP_SURPRISE), FLAG(t, PCI_EXP_LNKCAP_DLLA), diff --git a/tests/cap-address-xlation b/tests/cap-address-xlation index 75c02b9..493a634 100644 --- a/tests/cap-address-xlation +++ b/tests/cap-address-xlation @@ -20,7 +20,7 @@ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited - ClockPM- Suprise- LLActRep- BwNot- + ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- diff --git a/tests/cap-pcie-1 b/tests/cap-pcie-1 index f9621a0..da5df1e 100644 --- a/tests/cap-pcie-1 +++ b/tests/cap-pcie-1 @@ -21,7 +21,7 @@ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x4, ASPM unknown, Latency L0 <512ns, L1 <4us - ClockPM- Suprise+ LLActRep+ BwNot+ + ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- diff --git a/tests/cap-pcie-2 b/tests/cap-pcie-2 index 5221bd0..a50a3b9 100644 --- a/tests/cap-pcie-2 +++ b/tests/cap-pcie-2 @@ -25,7 +25,7 @@ MaxPayload 256 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <4us, L1 <64us - ClockPM- Suprise- LLActRep- BwNot- + ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-