--- /dev/null
+#include "util.h"
+#include "modbus.h"
+
+#include <libopencm3/cm3/nvic.h>
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/usart.h>
+#include <libopencm3/stm32/timer.h>
+
+enum mb_state {
+ STATE_RX,
+ STATE_RX_DONE,
+ STATE_PROCESSING,
+ STATE_TX,
+ STATE_TX_LAST,
+ STATE_TX_DONE,
+};
+
+#define RX_BUFSIZE 256
+#define TX_BUFSIZE 256
+
+static byte rx_buf[RX_BUFSIZE];
+static u16 rx_size;
+static byte rx_bad;
+static byte state; // STATE_xxx
+
+static byte tx_buf[TX_BUFSIZE];
+static u16 tx_size;
+static u16 tx_pos;
+
+#define MB_OUR_ADDRESS 42
+
+static void UNUSED xx_write_char(uint c) // FIXME
+{
+ usart_set_mode(USART2, USART_MODE_TX);
+ gpio_set(GPIOA, GPIO1);
+ usart_send_blocking(USART2, c);
+ while (!usart_get_flag(USART2, USART_SR_TC))
+ ;
+ gpio_clear(GPIOA, GPIO1);
+ usart_set_mode(USART2, USART_MODE_RX);
+}
+
+static void rx_init(void)
+{
+ state = STATE_RX;
+ rx_size = 0;
+ rx_bad = 0;
+ usart_set_mode(USART2, USART_MODE_RX);
+ usart_enable_rx_interrupt(USART2);
+}
+
+static void rx_done(void)
+{
+ state = STATE_RX_DONE;
+ usart_disable_rx_interrupt(USART2);
+}
+
+static void tx_init(void)
+{
+ state = STATE_TX;
+ tx_pos = 0;
+ gpio_set(GPIOA, GPIO1);
+ usart_set_mode(USART2, USART_MODE_TX);
+ usart_enable_tx_interrupt(USART2);
+}
+
+static void tx_done(void)
+{
+ state = STATE_TX_DONE;
+ // usart_disable_tx_interrupt(USART2); // Already done by irq handler
+ gpio_clear(GPIOA, GPIO1);
+}
+
+void modbus_init(void)
+{
+ timer_set_prescaler(TIM2, 71); // 1 tick = 1 μs
+ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_DOWN);
+ timer_update_on_overflow(TIM2);
+ timer_disable_preload(TIM2);
+ timer_one_shot_mode(TIM2);
+ timer_enable_irq(TIM2, TIM_DIER_UIE);
+ nvic_enable_irq(NVIC_TIM2_IRQ);
+
+ gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_USART2_RX);
+ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX);
+
+ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO1);
+ gpio_clear(GPIOA, GPIO1);
+
+ usart_set_baudrate(USART2, 19200);
+ usart_set_databits(USART2, 8);
+ usart_set_stopbits(USART2, USART_STOPBITS_1);
+ usart_set_parity(USART2, USART_PARITY_NONE);
+ // usart_set_parity(USART2, USART_PARITY_EVEN); // FIXME
+ usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE);
+
+ rx_init();
+
+ nvic_enable_irq(NVIC_USART2_IRQ);
+ usart_enable(USART2);
+
+#if 0
+ u32 xxx = USART_CR1(USART2);
+ usart_set_mode(USART2, USART_MODE_TX);
+ gpio_set(GPIOA, GPIO1);
+ debug_printf("%08x\n", xxx);
+ xx_write_char('\n');
+#endif
+}
+
+void usart2_isr(void)
+{
+ u32 status = USART_SR(USART2);
+
+ // FIXME: Optimize
+
+ if (status & USART_SR_RXNE) {
+ uint ch = usart_recv(USART2);
+ if (state == STATE_RX) {
+#if 0
+ if (status & (USART_SR_FE | USART_SR_ORE | USART_SR_NE)) {
+ rx_bad = 1;
+ } else
+#endif
+ if (rx_size < RX_BUFSIZE) {
+ rx_buf[rx_size++] = ch;
+ } else {
+ // Frame too long
+ rx_bad = 2;
+ }
+ timer_set_period(TIM2, 7500); // 0.75 ms timeout for end of frame (FIXME: right value?)
+ timer_generate_event(TIM2, TIM_EGR_UG);
+ timer_enable_counter(TIM2);
+ }
+ }
+
+ if (state == STATE_TX) {
+ if (status & USART_SR_TXE) {
+ if (tx_pos < tx_size) {
+ usart_send(USART2, tx_buf[tx_pos++]);
+ } else {
+ // The transmitter is double-buffered, so at this moment, it is transmitting
+ // the last byte of the frame. Wait until transfer is completed.
+ usart_disable_tx_interrupt(USART2);
+ USART_CR1(USART2) |= USART_CR1_TCIE;
+ state = STATE_TX_LAST;
+ }
+ }
+ }
+
+ if (state == STATE_TX_LAST) {
+ if (status & USART_SR_TC) {
+ // Transfer of the last byte is complete. Release the bus.
+ USART_CR1(USART2) &= ~USART_CR1_TCIE;
+ tx_done();
+ rx_init();
+ }
+ }
+}
+
+void tim2_isr(void)
+{
+ if (TIM_SR(TIM2) & TIM_SR_UIF) {
+ TIM_SR(TIM2) &= ~TIM_SR_UIF;
+ if (state == STATE_RX)
+ rx_done();
+ }
+}
+
+// CRC tables
+
+static const byte crc_hi[] = {
+ 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41, 0x01, 0xc0,
+ 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41,
+ 0x00, 0xc1, 0x81, 0x40, 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0,
+ 0x80, 0x41, 0x01, 0xc0, 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40,
+ 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41, 0x00, 0xc1,
+ 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41, 0x01, 0xc0, 0x80, 0x41,
+ 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41, 0x00, 0xc1,
+ 0x81, 0x40, 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41,
+ 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41, 0x01, 0xc0,
+ 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40, 0x00, 0xc1, 0x81, 0x40,
+ 0x01, 0xc0, 0x80, 0x41, 0x01, 0xc0, 0x80, 0x41, 0x00, 0xc1,
+ 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40,
+ 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41, 0x01, 0xc0,
+ 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40, 0x00, 0xc1, 0x81, 0x40,
+ 0x01, 0xc0, 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0,
+ 0x80, 0x41, 0x01, 0xc0, 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40,
+ 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41, 0x01, 0xc0,
+ 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41,
+ 0x00, 0xc1, 0x81, 0x40, 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0,
+ 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41,
+ 0x01, 0xc0, 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0,
+ 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40, 0x00, 0xc1, 0x81, 0x40,
+ 0x01, 0xc0, 0x80, 0x41, 0x01, 0xc0, 0x80, 0x41, 0x00, 0xc1,
+ 0x81, 0x40, 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41,
+ 0x00, 0xc1, 0x81, 0x40, 0x01, 0xc0, 0x80, 0x41, 0x01, 0xc0,
+ 0x80, 0x41, 0x00, 0xc1, 0x81, 0x40
+};
+
+static const byte crc_lo[] = {
+ 0x00, 0xc0, 0xc1, 0x01, 0xc3, 0x03, 0x02, 0xc2, 0xc6, 0x06,
+ 0x07, 0xc7, 0x05, 0xc5, 0xc4, 0x04, 0xcc, 0x0c, 0x0d, 0xcd,
+ 0x0f, 0xcf, 0xce, 0x0e, 0x0a, 0xca, 0xcb, 0x0b, 0xc9, 0x09,
+ 0x08, 0xc8, 0xd8, 0x18, 0x19, 0xd9, 0x1b, 0xdb, 0xda, 0x1a,
+ 0x1e, 0xde, 0xdf, 0x1f, 0xdd, 0x1d, 0x1c, 0xdc, 0x14, 0xd4,
+ 0xd5, 0x15, 0xd7, 0x17, 0x16, 0xd6, 0xd2, 0x12, 0x13, 0xd3,
+ 0x11, 0xd1, 0xd0, 0x10, 0xf0, 0x30, 0x31, 0xf1, 0x33, 0xf3,
+ 0xf2, 0x32, 0x36, 0xf6, 0xf7, 0x37, 0xf5, 0x35, 0x34, 0xf4,
+ 0x3c, 0xfc, 0xfd, 0x3d, 0xff, 0x3f, 0x3e, 0xfe, 0xfa, 0x3a,
+ 0x3b, 0xfb, 0x39, 0xf9, 0xf8, 0x38, 0x28, 0xe8, 0xe9, 0x29,
+ 0xeb, 0x2b, 0x2a, 0xea, 0xee, 0x2e, 0x2f, 0xef, 0x2d, 0xed,
+ 0xec, 0x2c, 0xe4, 0x24, 0x25, 0xe5, 0x27, 0xe7, 0xe6, 0x26,
+ 0x22, 0xe2, 0xe3, 0x23, 0xe1, 0x21, 0x20, 0xe0, 0xa0, 0x60,
+ 0x61, 0xa1, 0x63, 0xa3, 0xa2, 0x62, 0x66, 0xa6, 0xa7, 0x67,
+ 0xa5, 0x65, 0x64, 0xa4, 0x6c, 0xac, 0xad, 0x6d, 0xaf, 0x6f,
+ 0x6e, 0xae, 0xaa, 0x6a, 0x6b, 0xab, 0x69, 0xa9, 0xa8, 0x68,
+ 0x78, 0xb8, 0xb9, 0x79, 0xbb, 0x7b, 0x7a, 0xba, 0xbe, 0x7e,
+ 0x7f, 0xbf, 0x7d, 0xbd, 0xbc, 0x7c, 0xb4, 0x74, 0x75, 0xb5,
+ 0x77, 0xb7, 0xb6, 0x76, 0x72, 0xb2, 0xb3, 0x73, 0xb1, 0x71,
+ 0x70, 0xb0, 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92,
+ 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54, 0x9c, 0x5c,
+ 0x5d, 0x9d, 0x5f, 0x9f, 0x9e, 0x5e, 0x5a, 0x9a, 0x9b, 0x5b,
+ 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89, 0x4b, 0x8b,
+ 0x8a, 0x4a, 0x4e, 0x8e, 0x8f, 0x4f, 0x8d, 0x4d, 0x4c, 0x8c,
+ 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42,
+ 0x43, 0x83, 0x41, 0x81, 0x80, 0x40
+};
+
+static u16 crc16(byte *buf, u16 len)
+{
+ byte hi = 0xff, lo = 0xff;
+
+ while (len--) {
+ byte i = hi ^ *buf++;
+ hi = lo ^ crc_hi[i];
+ lo = crc_lo[i];
+ }
+
+ return (hi << 8 | lo);
+}
+
+static bool check_frame(void)
+{
+ if (rx_bad) {
+ // FIXME: Error counters?
+ return false;
+ }
+
+ if (rx_size < 4) {
+ // FIXME: Error counters?
+ return false;
+ }
+
+ u16 crc = crc16(rx_buf, rx_size - 2);
+ u16 rx_crc = (rx_buf[rx_size-2] << 8) | rx_buf[rx_size-1];
+ if (crc != rx_crc) {
+ // FIXME: Error counters?
+ return false;
+ }
+
+ return true;
+}
+
+enum mb_function {
+ FUNC_READ_HOLDING_REGISTERS = 0x03,
+};
+
+enum mb_error {
+ ERR_ILLEGAL_FUNCTION = 0x01,
+ ERR_ILLEGAL_DATA_ADDRESS = 0x02,
+ ERR_ILLEGAL_DATA_VALUE = 0x03,
+};
+
+static void report_error(byte code)
+{
+ // Discard the partially constructed body of the reply and rewrite the header
+ tx_buf[1] |= 0x80;
+ tx_buf[2] = code;
+ tx_size = 3;
+}
+
+static void process_frame(void)
+{
+ byte func = rx_buf[1];
+
+ // Prepare reply frame
+ tx_buf[0] = MB_OUR_ADDRESS;
+ tx_buf[1] = rx_buf[1];
+ tx_size = 2;
+
+ switch (func) {
+ case FUNC_READ_HOLDING_REGISTERS:
+ tx_buf[tx_size++] = 2;
+ tx_buf[tx_size++] = 0x12;
+ tx_buf[tx_size++] = 0x34;
+ break;
+ default:
+ report_error(ERR_ILLEGAL_FUNCTION);
+ }
+
+ // Finish reply frame
+ u16 crc = crc16(tx_buf, tx_size);
+ tx_buf[tx_size++] = crc >> 8;
+ tx_buf[tx_size++] = crc;
+}
+
+void modbus_loop(void)
+{
+ if (state != STATE_RX_DONE) {
+ // gpio_toggle(GPIOC, GPIO13);
+ return;
+ }
+ state = STATE_PROCESSING;
+ gpio_toggle(GPIOC, GPIO13);
+
+ if (!check_frame()) {
+ rx_init();
+ return;
+ }
+
+ if (rx_buf[0] == MB_OUR_ADDRESS) {
+ // Frame addressed to us: process and reply
+ process_frame();
+ tx_init();
+ } else if (rx_buf[0] == 0x00) {
+ // Broadcast frame: process, but do not reply
+ process_frame();
+ rx_init();
+ } else {
+ // Somebody else's frame: discard
+ rx_init();
+ }
+}