(no commit message)

diff --git a/ChangeLog b/ChangeLog
index 6f1836c23d9488a11e14e268dcd04e6f79e58e5a..721f96ffffcf08dbff8af7919a839ef3cd1f4244 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,7 @@
 2006-07-30  Martin Mares  <mj@ucw.cz>
 
+       * lib/header.h: Whitespace cleanups.
+
        * lib/i386-io-windows.h: Fixed indentation and spelling.
 
        * README.Windows: Mention that WinIO.dll is needed and where to get it.

diff --git a/lib/header.h b/lib/header.h
index f064ab8afd821d168a7b059f694b4a9c32006dde..ab562142358fbe755af17c642569298b63f1671e 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -31,7 +31,7 @@
 #define  PCI_STATUS_FAST_BACK  0x80    /* Accept fast-back to back */
 #define  PCI_STATUS_PARITY     0x100   /* Detected parity error */
 #define  PCI_STATUS_DEVSEL_MASK        0x600   /* DEVSEL timing */
-#define  PCI_STATUS_DEVSEL_FAST        0x000   
+#define  PCI_STATUS_DEVSEL_FAST        0x000
 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
 #define  PCI_STATUS_DEVSEL_SLOW 0x400
 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
@@ -60,8 +60,8 @@
 
 /*
  * Base addresses specify locations in memory or I/O space.
- * Decoded size can be determined by writing a value of 
- * 0xffffffff to the register, and reading it back.  Only 
+ * Decoded size can be determined by writing a value of
+ * 0xffffffff to the register, and reading it back.  Only
  * 1 bits are decoded.
  */
 #define PCI_BASE_ADDRESS_0     0x10    /* 32 bits */
@@ -85,7 +85,7 @@
 /* Header type 0 (normal devices) */
 #define PCI_CARDBUS_CIS                0x28
 #define PCI_SUBSYSTEM_VENDOR_ID        0x2c
-#define PCI_SUBSYSTEM_ID       0x2e  
+#define PCI_SUBSYSTEM_ID       0x2e
 #define PCI_ROM_ADDRESS                0x30    /* Bits 31..11 are address, 10..1 reserved */
 #define  PCI_ROM_ADDRESS_ENABLE        0x01
 #define PCI_ROM_ADDRESS_MASK   (~(pciaddr_t)0x7ff)
@@ -285,7 +285,7 @@
 #define PCI_PCIX_COMMAND_DPERE                                     0x0001 /* Data Parity Error Recover Enable */
 #define PCI_PCIX_COMMAND_ERO                                       0x0002 /* Enable Relaxed Ordering */
 #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT                   0x000c /* Maximum Memory Read Byte Count */
-#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS               0x0070  
+#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS               0x0070
 #define PCI_PCIX_COMMAND_RESERVED                                   0xf80
 #define PCI_PCIX_STATUS                                                 4 /* Status register offset */
 #define PCI_PCIX_STATUS_FUNCTION                               0x00000007