#define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */
#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
+/*** Definitions of capabilities ***/
+
/* Power Management Registers */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
#define PCI_AF_STATUS 5
#define PCI_AF_STATUS_TP 0x01
+/* SATA Host Bus Adapter */
+#define PCI_SATA_HBA_BARS 4
+#define PCI_SATA_HBA_REG0 8
+
+/*** Definitions of extended capabilities ***/
+
/* Advanced Error Reporting */
#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
#define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */
printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
}
+static void
+cap_sata_hba(struct device *d, int where, int cap)
+{
+ u32 bars;
+ int bar;
+
+ printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
+ if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
+ {
+ printf("\n");
+ return;
+ }
+
+ bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
+ bar = BITS(bars, 0, 4);
+ if (bar >= 4 && bar <= 9)
+ printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
+ else if (bar == 15)
+ printf(" InCfgSpace\n");
+ else
+ printf(" BAR??%d\n", bar);
+}
+
void
show_caps(struct device *d)
{
cap_msix(d, where, cap);
break;
case PCI_CAP_ID_SATA:
- printf("SATA HBA <?>\n");
+ cap_sata_hba(d, where, cap);
break;
case PCI_CAP_ID_AF:
cap_af(d, where);