lspci: Decode AER Multiple Header and TLP Prefix Log bits

Decode the AER Multiple Header Recording and TLP Prefix Log Present bits in
the AER Capabilities and Control register.

The difference in the "lspci -vv" output looks like this:

-       AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+       AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+               MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/lib/header.h b/lib/header.h
index 6d81cb71f742cce0a84f17dc53b6f89aa9f167d1..f031e371a458180b2859079cf124b946a254b7e1 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -958,6 +958,10 @@
 #define  PCI_ERR_CAP_ECRC_GENE 0x00000040      /* ECRC Generation Enable */
 #define  PCI_ERR_CAP_ECRC_CHKC 0x00000080      /* ECRC Check Capable */
 #define  PCI_ERR_CAP_ECRC_CHKE 0x00000100      /* ECRC Check Enable */
+#define  PCI_ERR_CAP_MULT_HDRC 0x00000200      /* Multiple Header Capable */
+#define  PCI_ERR_CAP_MULT_HDRE 0x00000400      /* Multiple Header Enable */
+#define  PCI_ERR_CAP_TLP_PFX   0x00000800      /* TLP Prefix Log Present */
+#define  PCI_ERR_CAP_HDR_LOG   0x00001000      /* Completion Timeout Prefix/Header Log Capable */
 #define PCI_ERR_HEADER_LOG     28      /* Header Log Register (16 bytes) */
 #define PCI_ERR_ROOT_COMMAND   44      /* Root Error Command */
 #define PCI_ERR_ROOT_STATUS    48

diff --git a/ls-ecaps.c b/ls-ecaps.c
index fdb98aa751a7beacfd6e187f457dcd096244fbea..ce3c61394a0e93895feae3d9b1cb2832685f5cfe 100644 (file)
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -131,10 +131,12 @@ cap_aer(struct device *d, int where)
        FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
        FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
   l = get_conf_long(d, where + PCI_ERR_CAP);
-  printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n",
+  printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n"
+       "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
        PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
-       FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE));
-
+       FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
+       FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
+       FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
 }
 
 static void cap_dpc(struct device *d, int where)

diff --git a/tests/cap-aer-hdr b/tests/cap-aer-hdr
new file mode 100644 (file)
index 0000000..198f9dc
--- /dev/null
+++ b/tests/cap-aer-hdr
@@ -0,0 +1,322 @@
+00:1c.0 PCI bridge: Intel Corporation Device 9d10 (rev f1) (prog-if 00 [Normal decode])
+       Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+       Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+       Latency: 0
+       Interrupt: pin A routed to IRQ 255
+       Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
+       I/O behind bridge: None
+       Memory behind bridge: f1100000-f11fffff [size=1M]
+       Prefetchable memory behind bridge: None
+       Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
+       BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
+               PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
+       Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
+               DevCap: MaxPayload 256 bytes, PhantFunc 0
+                       ExtTag- RBE+
+               DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+                       RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+                       MaxPayload 256 bytes, MaxReadReq 128 bytes
+               DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
+               LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L0s <1us, L1 <16us
+                       ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
+               LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+
+                       ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+               LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
+               SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
+                       Slot #0, PowerLimit 10.000W; Interlock- NoCompl+
+               SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
+                       Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
+               SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+                       Changed: MRL- PresDet- LinkState+
+               RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
+               RootCap: CRSVisible-
+               RootSta: PME ReqID 0000, PMEStatus- PMEPending-
+               DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
+               AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
+               DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
+               AtomicOpsCtl: ReqEn- EgressBlck-
+               LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+                        Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+                        Compliance De-emphasis: -6dB
+               LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+                        EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+       Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit-
+               Address: 00000000  Data: 0000
+       Capabilities: [90] Subsystem: Lenovo Device 2238
+       Capabilities: [a0] Power Management version 3
+               Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
+               Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+       Capabilities: [100 v1] Advanced Error Reporting
+               UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+               UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt+ RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+               UESvrt: DLP+ SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+               CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+               CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+               AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
+                       MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+       Capabilities: [140 v1] Access Control Services
+               ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans-
+               ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
+       Capabilities: [200 v1] L1 PM Substates
+               L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
+                         PortCommonModeRestoreTime=40us PortTPowerOnTime=10us
+               L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
+                          T_CommonMode=60us LTR1.2_Threshold=163840ns
+               L1SubCtl2: T_PwrOn=60us
+       Capabilities: [220 v1] #19
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+10: 00 00 00 00 00 00 00 00 00 02 02 00 f0 00 00 20
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+30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 00 00
+40: 10 80 42 01 01 80 00 00 20 00 10 00 13 48 72 01
+50: 42 00 12 70 00 b2 04 00 00 00 40 01 00 00 00 00
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+d0: 11 10 00 07 42 18 00 00 08 00 9e 8b 00 00 00 00
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+f0: 50 01 00 00 00 03 00 40 b3 0f 30 08 04 00 00 01
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