}
// Pull line down and start timer
- cm_disable_interrupts();
timer_generate_event(DS_TIMER, TIM_EGR_UG);
- timer_enable_counter(DS_TIMER);
timer_set_oc_mode(DS_TIMER, TIM_OC2, TIM_OCM_INACTIVE);
- cm_enable_interrupts();
+ timer_enable_counter(DS_TIMER);
// Wait until the timer expires
while (timer_is_counter_enabled(DS_TIMER))
timer_set_period(DS_TIMER, 99); // Each write slot takes 100 μs
timer_set_oc_mode(DS_TIMER, TIM_OC2, TIM_OCM_FORCE_HIGH);
timer_set_oc_value(DS_TIMER, TIM_OC2, (bit ? 3 : 89)); // 1: 3μs pulse, 0: 89μs pulse
- cm_disable_interrupts();
- // XXX: On STM32F1, we must configure the OC channel _after_ we enable the counter,
- // otherwise OC triggers immediately. Reasons?
- timer_enable_counter(DS_TIMER);
+ timer_generate_event(DS_TIMER, TIM_EGR_UG);
timer_set_oc_mode(DS_TIMER, TIM_OC2, TIM_OCM_INACTIVE);
- cm_enable_interrupts();
+ timer_enable_counter(DS_TIMER);
while (timer_is_counter_enabled(DS_TIMER))
;
}
dma_set_number_of_data(DS_DMA, DS_DMA_CH, 1);
dma_enable_channel(DS_DMA, DS_DMA_CH);
timer_set_oc_mode(DS_TIMER, TIM_OC2, TIM_OCM_FORCE_HIGH);
- cm_disable_interrupts();
- timer_enable_counter(DS_TIMER);
+ timer_generate_event(DS_TIMER, TIM_EGR_UG);
timer_set_oc_mode(DS_TIMER, TIM_OC2, TIM_OCM_INACTIVE);
- cm_enable_interrupts();
+ timer_enable_counter(DS_TIMER);
while (timer_is_counter_enabled(DS_TIMER))
;
// DEBUG2("XXX %08x\n", ds_dma_buffer);