lspci: Add support for CXL Flex Bus DVSEC

Add DVSEC Flex Bus Port for CXL devices according to DVSEC Revision ID 1,
capability decoding, control decoding, and status decoding.

Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>

diff --git a/lib/header.h b/lib/header.h
index 36b7040affdce70f1b08085e41d8cfaee2c06858..cc69a5189be93e707d970a9462bcc3de3a130a35 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -1142,6 +1142,46 @@
 #define PCI_CXL_GPF_DEV_1S      0x6
 #define PCI_CXL_GPF_DEV_10S     0x7
 
+/* PCIe CXL Designated Vendor-Specific Capabilities for Flex Bus Port */
+#define PCI_CXL_FB_LEN                0x20
+#define PCI_CXL_FB_PORT_CAP           0x0a    /* CXL Flex Bus Port Capability Register */
+#define  PCI_CXL_FB_CAP_CACHE         0x0001  /* CXL.cache Capable */
+#define  PCI_CXL_FB_CAP_IO            0x0002  /* CXL.io Capable */
+#define  PCI_CXL_FB_CAP_MEM           0x0004  /* CXL.mem Capable */
+#define  PCI_CXL_FB_CAP_68B_FLIT      0x0020  /* CXL 68B Flit and VH Capable */
+#define  PCI_CXL_FB_CAP_MULT_LOG_DEV  0x0040  /* CXL Multi-Logical Device Capable */
+#define  PCI_CXL_FB_CAP_256B_FLIT     0x2000  /* CXL Latency Optimized 256B Flit Capable */
+#define  PCI_CXL_FB_CAP_PBR_FLIT      0x4000  /* CXL PBR Flit Capable */
+#define PCI_CXL_FB_PORT_CTRL            0x0c    /* CXL Flex Bus Port Control Register */
+#define  PCI_CXL_FB_CTRL_CACHE          0x0001  /* CXL.cache Enable */
+#define  PCI_CXL_FB_CTRL_IO             0x0002  /* CXL.io Enable */
+#define  PCI_CXL_FB_CTRL_MEM            0x0004  /* CXL.mem Enable */
+#define  PCI_CXL_FB_CTRL_SYNC_HDR_BYP   0x0008  /* CXL Sync Header Bypass Enable */
+#define  PCI_CXL_FB_CTRL_DRFT_BUF       0x0010  /* Drift Buffer Enable */
+#define  PCI_CXL_FB_CTRL_68B_FLIT       0x0020  /* CXL 68B Flit and VH Enable */
+#define  PCI_CXL_FB_CTRL_MULT_LOG_DEV   0x0040  /* CXL Multi Logical Device Enable */
+#define  PCI_CXL_FB_CTRL_RCD            0x0080  /* Disable RCD Training */
+#define  PCI_CXL_FB_CTRL_RETIMER1       0x0100  /* Retimer1 Present */
+#define  PCI_CXL_FB_CTRL_RETIMER2       0x0200  /* Retimer2 Present */
+#define  PCI_CXL_FB_CTRL_256B_FLIT      0x2000  /* CXL Latency Optimized 256B Flit Enable */
+#define  PCI_CXL_FB_CTRL_PBR_FLIT       0x4000  /* CXL PBR Flit Enable */
+#define PCI_CXL_FB_PORT_STATUS            0x0e    /* CXL Flex Bus Port Status Register */
+#define  PCI_CXL_FB_STAT_CACHE            0x0001  /* CXL.cache Enabled */
+#define  PCI_CXL_FB_STAT_IO               0x0002  /* CXL.io Enabled */
+#define  PCI_CXL_FB_STAT_MEM              0x0004  /* CXL.mem Enabled */
+#define  PCI_CXL_FB_STAT_SYNC_HDR_BYP     0x0008  /* CXL Sync Header Bypass Enabled */
+#define  PCI_CXL_FB_STAT_DRFT_BUF         0x0010  /* Drift Buffer Enabled */
+#define  PCI_CXL_FB_STAT_68B_FLIT         0x0020  /* CXL 68B Flit and VH Enabled */
+#define  PCI_CXL_FB_STAT_MULT_LOG_DEV     0x0040  /* CXL Multi Logical Device Enabled */
+#define  PCI_CXL_FB_STAT_256B_FLIT        0x2000  /* CXL Latency Optimized 256B Flit Enabled */
+#define  PCI_CXL_FB_STAT_PBR_FLIT         0x4000  /* CXL PBR Flit Enabled */
+#define PCI_CXL_FB_MOD_TS_DATA              0x10    /* CXL Flex Bus Port Received Modified TS Data Phase1 Register */
+#define PCI_CXL_FB_PORT_CAP2                0x14    /* CXL Flex Bus Port Capability2 Register */
+#define  PCI_CXL_FB_CAP2_NOP_HINT           0x01    /* NOP Hint Capable */
+#define PCI_CXL_FB_PORT_CTRL2               0x18    /* CXL Flex Bus Port Control2 Register */
+#define  PCI_CXL_FB_CTRL2_NOP_HINT          0x01    /* NOP Hint Enable */
+#define PCI_CXL_FB_PORT_STATUS2             0x1c    /* CXL Flex Bus Port Status2 Register */
+
 /* Access Control Services */
 #define PCI_ACS_CAP            0x04    /* ACS Capability Register */
 #define PCI_ACS_CAP_VALID      0x0001  /* ACS Source Validation */

diff --git a/ls-ecaps.c b/ls-ecaps.c
index af71c63689bf19e41af7d9a8a4e2780b1e778330..abfc30c3b0b1fc00c15b0ac65a326bd3aaf50ba2 100644 (file)
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -880,6 +880,71 @@ dvsec_cxl_gpf_device(struct device *d, int where)
   printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l);
 }
 
+static void
+dvsec_cxl_flex_bus(struct device *d, int where, int rev)
+{
+  u16 w;
+  u32 l, data;
+
+  if (rev < 1)
+  {
+    printf("\t\tRevision %d not supported\n", rev);
+    return;
+  }
+
+  w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP);
+  printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c",
+      FLAG(w, PCI_CXL_FB_CAP_CACHE), FLAG(w, PCI_CXL_FB_CAP_IO),
+      FLAG(w, PCI_CXL_FB_CAP_MEM), FLAG(w, PCI_CXL_FB_CAP_68B_FLIT),
+      FLAG(w, PCI_CXL_FB_CAP_MULT_LOG_DEV));
+
+  if (rev > 1)
+    printf(" 256BFlit%c PBRFlit%c",
+        FLAG(w, PCI_CXL_FB_CAP_256B_FLIT), FLAG(w, PCI_CXL_FB_CAP_PBR_FLIT));
+
+  w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL);
+  printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c",
+      FLAG(w, PCI_CXL_FB_CTRL_CACHE), FLAG(w, PCI_CXL_FB_CTRL_IO),
+      FLAG(w, PCI_CXL_FB_CTRL_MEM), FLAG(w, PCI_CXL_FB_CTRL_SYNC_HDR_BYP),
+      FLAG(w, PCI_CXL_FB_CTRL_DRFT_BUF), FLAG(w, PCI_CXL_FB_CTRL_68B_FLIT),
+      FLAG(w, PCI_CXL_FB_CTRL_MULT_LOG_DEV), FLAG(w, PCI_CXL_FB_CTRL_RCD),
+      FLAG(w, PCI_CXL_FB_CTRL_RETIMER1), FLAG(w, PCI_CXL_FB_CTRL_RETIMER2));
+
+  if (rev > 1)
+    printf(" 256BFlit%c PBRFlit%c",
+        FLAG(w, PCI_CXL_FB_CTRL_256B_FLIT), FLAG(w, PCI_CXL_FB_CTRL_PBR_FLIT));
+
+  w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS);
+  printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c",
+      FLAG(w, PCI_CXL_FB_STAT_CACHE), FLAG(w, PCI_CXL_FB_STAT_IO),
+      FLAG(w, PCI_CXL_FB_STAT_MEM), FLAG(w, PCI_CXL_FB_STAT_SYNC_HDR_BYP),
+      FLAG(w, PCI_CXL_FB_STAT_DRFT_BUF), FLAG(w, PCI_CXL_FB_STAT_68B_FLIT),
+      FLAG(w, PCI_CXL_FB_STAT_MULT_LOG_DEV));
+
+  if (rev > 1)
+    printf(" 256BFlit%c PBRFlit%c",
+        FLAG(w, PCI_CXL_FB_STAT_256B_FLIT), FLAG(w, PCI_CXL_FB_STAT_PBR_FLIT));
+
+  l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA);
+  data = BITS(l, 0, 24);
+  printf("\n\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data);
+
+  if (rev > 1)
+  {
+    u8 nop;
+
+    l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2);
+    printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT));
+
+    l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2);
+    printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT));
+
+    l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2);
+    nop = BITS(l, 0, 2);
+    printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop);
+    }
+}
+
 static void
 cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
 {
@@ -908,7 +973,7 @@ cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
       dvsec_cxl_gpf_device(d, where);
       break;
     case 7:
-      printf("\t\tPCIe DVSEC Flex Bus Port\n");
+      dvsec_cxl_flex_bus(d, where, rev);
       break;
     case 8:
       dvsec_cxl_register_locator(d, where, len);