Originally, we guessed based on CPU model, but as I have ripped out
model detection, we cannot do that any longer; besides, it was very
much out of date.
Now, we use simple heuristics: anybody caring about performance
runs on amd64 and all amd64 processors have large enough L1 cache
to use 12-bit bucket width.
Set("CONFIG_UCW_POOL_IS_MMAP");
# Guess optimal bit width of the radix-sorter
-if (Get("CPU_ARCH") eq "default" || Get("CPU_ARCH") =~ /^i[345]86$/) {
- # This should be safe everywhere
- Set("CONFIG_UCW_RADIX_SORTER_BITS" => 10);
-} else {
- # Use this on modern CPU's
- Set("CONFIG_UCW_RADIX_SORTER_BITS" => 12);
-}
+Test("CONFIG_UCW_RADIX_SORTER_BITS", "Determining radix sorter bucket width", sub {
+ if (Get("CPU_AMD64")) {
+ # All amd64 CPUs have large enough L1 cache
+ return 12;
+ } else {
+ # This should be safe everywhere
+ return 10;
+ }
+});
# Detect if thread-local storage is supported
if (Get("CONFIG_UCW_THREADS")) {