]> mj.ucw.cz Git - home-hw.git/commitdiff
ir-send: experiments
authorMartin Mares <mj@ucw.cz>
Thu, 11 Jul 2019 21:53:50 +0000 (23:53 +0200)
committerMartin Mares <mj@ucw.cz>
Thu, 11 Jul 2019 21:53:50 +0000 (23:53 +0200)
ir-send/Makefile [new file with mode: 0644]
ir-send/config.h [new file with mode: 0644]
ir-send/test.c [new file with mode: 0644]

diff --git a/ir-send/Makefile b/ir-send/Makefile
new file mode 100644 (file)
index 0000000..81ed48b
--- /dev/null
@@ -0,0 +1,9 @@
+ROOT=..
+BINARY=test
+OBJS=test.o
+LIB_OBJS=util-debug.o
+
+WITH_BOOT_LOADER=1
+WITH_DFU_FLASH=1
+
+include $(ROOT)/mk/bluepill.mk
diff --git a/ir-send/config.h b/ir-send/config.h
new file mode 100644 (file)
index 0000000..bdfda60
--- /dev/null
@@ -0,0 +1,7 @@
+// Processor clock
+
+#define CPU_CLOCK_MHZ 72
+
+// Debugging port
+
+#define DEBUG_USART USART1
diff --git a/ir-send/test.c b/ir-send/test.c
new file mode 100644 (file)
index 0000000..db52d8c
--- /dev/null
@@ -0,0 +1,112 @@
+#include "util.h"
+
+#include <libopencm3/cm3/cortex.h>
+#include <libopencm3/cm3/nvic.h>
+#include <libopencm3/cm3/systick.h>
+#include <libopencm3/stm32/rcc.h>
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/usart.h>
+#include <libopencm3/stm32/timer.h>
+
+static void clock_setup(void)
+{
+       rcc_clock_setup_in_hse_8mhz_out_72mhz();
+
+       rcc_periph_clock_enable(RCC_GPIOA);
+       rcc_periph_clock_enable(RCC_GPIOB);
+       rcc_periph_clock_enable(RCC_GPIOC);
+       rcc_periph_clock_enable(RCC_USART1);
+       rcc_periph_clock_enable(RCC_TIM2);
+       rcc_periph_clock_enable(RCC_AFIO);
+
+       rcc_periph_reset_pulse(RST_GPIOA);
+       rcc_periph_reset_pulse(RST_GPIOB);
+       rcc_periph_reset_pulse(RST_GPIOC);
+       rcc_periph_reset_pulse(RST_USART1);
+       rcc_periph_reset_pulse(RST_TIM2);
+}
+
+static void gpio_setup(void)
+{
+       // PC13 = BluePill LED
+       gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO13);
+       gpio_clear(GPIOC, GPIO13);
+
+       // Remap TIM2
+       // gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON, AFIO_MAPR_TIM2_REMAP_FULL_REMAP);
+       AFIO_MAPR = 0x04000300;
+}
+
+static volatile u32 ms_ticks;
+
+void sys_tick_handler(void)
+{
+       ms_ticks++;
+}
+
+static void tick_setup(void)
+{
+       systick_set_frequency(1000, 72000000);
+       systick_counter_enable();
+       systick_interrupt_enable();
+}
+
+static void delay_ms(uint ms)
+{
+       u32 start_ticks = ms_ticks;
+       while (ms_ticks - start_ticks < ms)
+               ;
+}
+
+static void usart_setup(void)
+{
+       gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART1_TX);
+
+       usart_set_baudrate(USART1, 115200);
+       usart_set_databits(USART1, 8);
+       usart_set_stopbits(USART1, USART_STOPBITS_1);
+       usart_set_mode(USART1, USART_MODE_TX_RX);
+       usart_set_parity(USART1, USART_PARITY_NONE);
+       usart_set_flow_control(USART1, USART_FLOWCONTROL_NONE);
+
+       usart_enable(USART1);
+}
+
+int main(void)
+{
+       clock_setup();
+       gpio_setup();
+       tick_setup();
+       usart_setup();
+
+       // cm_enable_interrupts();
+       debug_puts("Hello!\n");
+
+#if 1
+       timer_set_prescaler(TIM2, 3);
+       timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
+       timer_disable_preload(TIM2);
+       timer_set_period(TIM2, 65535);
+       timer_set_oc_mode(TIM2, TIM_OC3, TIM_OCM_PWM1);
+       timer_set_oc_value(TIM2, TIM_OC3, 32768);
+       timer_set_oc_polarity_high(TIM2, TIM_OC3);
+       timer_enable_counter(TIM2);
+       timer_enable_oc_output(TIM2, TIM_OC3);
+#endif
+
+       gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO10);
+       // gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO10);
+       gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO15);
+
+       for (;;) {
+               gpio_toggle(GPIOC, GPIO13);
+               delay_ms(20);
+               gpio_toggle(GPIOA, GPIO15);
+               debug_putc('.');
+               timer_set_oc_mode(TIM2, TIM_OC3, TIM_OCM_FORCE_LOW);
+               delay_ms(20);
+               timer_set_oc_mode(TIM2, TIM_OC3, TIM_OCM_FORCE_HIGH);
+       }
+
+       return 0;
+}