Fix spelling of surprise

It's surprise, not surpise or suprise.

Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>

diff --git a/ls-caps.c b/ls-caps.c
index 634dadce4e84834c80cd6cecbb9fee4637439108..507771a95ab139758a792a563bb081b4def0ef8c 100644 (file)
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -798,7 +798,7 @@ static void cap_express_slot(struct device *d, int where)
   u16 w;
 
   t = get_conf_long(d, where + PCI_EXP_SLTCAP);
-  printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
+  printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
        FLAG(t, PCI_EXP_SLTCAP_ATNB),
        FLAG(t, PCI_EXP_SLTCAP_PWRC),
        FLAG(t, PCI_EXP_SLTCAP_MRL),

diff --git a/tests/cap-pcie-1 b/tests/cap-pcie-1
index f82b71d4cee51c443ef54efa34dbace679d691d3..b69184fb8735b8641017b0951527a27dc75a5e73 100644 (file)
--- a/tests/cap-pcie-1
+++ b/tests/cap-pcie-1
@@ -21,11 +21,11 @@
                        MaxPayload 256 bytes, MaxReadReq 128 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                LnkCap: Port #1, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us
-                       ClockPM- Suprise+ LLActRep+ BwNot+
+                       ClockPM- Surprise+ LLActRep+ BwNot+
                LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
-               SltCap: AttnBtn+ PwrCtrl+ MRL+ AttnInd+ PwrInd+ HotPlug- Surpise-
+               SltCap: AttnBtn+ PwrCtrl+ MRL+ AttnInd+ PwrInd+ HotPlug- Surprise-
                        Slot # 40, PowerLimit 0.000000; Interlock+ NoCompl-
                SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
                        Control: AttnInd Off, PwrInd Off, Power+ Interlock-

diff --git a/tests/cap-pcie-2 b/tests/cap-pcie-2
index b7944a3f01a61d81852efe1caf73f3164f8d3e58..47c8953d9bf5d40c773a36abddaca833308d3a4d 100644 (file)
--- a/tests/cap-pcie-2
+++ b/tests/cap-pcie-2
@@ -26,7 +26,7 @@
                        MaxPayload 256 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend-
                LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <4us, L1 <64us
-                       ClockPM- Suprise- LLActRep- BwNot-
+                       ClockPM- Surprise- LLActRep- BwNot-
                LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-