More bits of PCIE capability decoding.

diff --git a/lib/header.h b/lib/header.h
index 1e74c05ee30b68b7c551e1d4d46b66af072bcee0..d820a0c2fae083fb09cadef2f57f4f89917b5102 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -1,7 +1,7 @@
 /*
  *     The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
  *
- *     Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz>
+ *     Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
  *
  *     Can be freely distributed and used under the terms of the GNU GPL.
  */
@@ -23,8 +23,10 @@
 #define  PCI_COMMAND_WAIT      0x80    /* Enable address/data stepping */
 #define  PCI_COMMAND_SERR      0x100   /* Enable SERR */
 #define  PCI_COMMAND_FAST_BACK 0x200   /* Enable back-to-back writes */
+#define  PCI_COMMAND_DISABLE_INTx      0x400   /* PCIE: Disable INTx interrupts */
 
 #define PCI_STATUS             0x06    /* 16 bits */
+#define  PCI_STATUS_INTx       0x08    /* PCIE: INTx interrupt pending */
 #define  PCI_STATUS_CAP_LIST   0x10    /* Support Capability List */
 #define  PCI_STATUS_66MHZ      0x20    /* Support 66 Mhz PCI 2.1 bus */
 #define  PCI_STATUS_UDF                0x40    /* Support User Definable Features [obsolete] */
@@ -136,6 +138,10 @@
 #define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
 #define  PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
 #define  PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
+#define  PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100                /* PCI-X? */
+#define  PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200                /* PCI-X? */
+#define  PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400     /* PCI-X? */
+#define  PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800    /* PCI-X? */
 
 /* Header type 2 (CardBus bridges) */
 /* 0x14-0x15 reserved */
@@ -692,6 +698,8 @@
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6   /* Downstream Port */
 #define  PCI_EXP_TYPE_PCI_BRIDGE 0x7   /* PCI/PCI-X Bridge */
 #define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8  /* PCI/PCI-X to PCIE Bridge */
+#define  PCI_EXP_TYPE_ROOT_INT_EP 0x9  /* Root Complex Integrated Endpoint */
+#define  PCI_EXP_TYPE_ROOT_EC 0xa      /* Root Complex Event Collector */
 #define PCI_EXP_FLAGS_SLOT     0x0100  /* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ      0x3e00  /* Interrupt message number */
 #define PCI_EXP_DEVCAP         0x4     /* Device capabilities */

diff --git a/lspci.c b/lspci.c
index d29da87e9b0254f313e7ddec8c2fa450b8985bff..f02219b2986e8e8639756f73778755b9cda1dd6a 100644 (file)
--- a/lspci.c
+++ b/lspci.c
@@ -1235,6 +1235,8 @@ show_express(struct device *d, int where, int cap)
   int slot = 0;
 
   printf("Express ");
+  if (verbose >= 2)
+    printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
   switch (type)
     {
     case PCI_EXP_TYPE_ENDPOINT:
@@ -1260,8 +1262,14 @@ show_express(struct device *d, int where, int cap)
     case PCI_EXP_TYPE_PCIE_BRIDGE:
       printf("PCI/PCI-X to PCI-Express Bridge");
       break;
+    case PCI_EXP_TYPE_ROOT_INT_EP:
+      printf("Root Complex Integrated Endpoint");
+      break;
+    case PCI_EXP_TYPE_ROOT_EC:
+      printf("Root Complex Event Collector");
+      break;
     default:
-      printf("Unknown type");
+      printf("Unknown type %d", type);
   }
   printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
   if (verbose < 2)