cxl: Rename caps to be device caps

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Co-authored-by: Jaxon Haws <jaxon.haws@amd.com>
Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>

diff --git a/lib/header.h b/lib/header.h
index 71f7fb0d0250af0ba0292b5f5d2244f7dbcd3406..1c269e51de2356d1b350a08146c3fe58a170452c 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -1068,25 +1068,25 @@
 #define PCI_DVSEC_VENDOR_ID_CXL        0x1e98  /* Designated Vendor-Specific Vendor ID for CXL */
 #define PCI_DVSEC_ID_CXL       0       /* Designated Vendor-Specific ID for Intel CXL */
 
-/* PCIe CXL Designated Vendor-Specific Capabilities, Control, Status */
+/* PCIe CXL Designated Vendor-Specific Capabilities for Devices: Control, Status */
 #define PCI_CXL_DEV_LEN 0x38 /* CXL Device DVSEC Length */
-#define PCI_CXL_CAP            0x0a    /* CXL Capability Register */
-#define  PCI_CXL_CAP_CACHE     0x0001  /* CXL.cache Protocol Support */
-#define  PCI_CXL_CAP_IO                0x0002  /* CXL.io Protocol Support */
-#define  PCI_CXL_CAP_MEM       0x0004  /* CXL.mem Protocol Support */
-#define  PCI_CXL_CAP_MEM_HWINIT        0x0008  /* CXL.mem Initializes with HW/FW Support */
-#define  PCI_CXL_CAP_HDM_CNT(x)        (((x) & (3 << 4)) >> 4) /* CXL Number of HDM ranges */
-#define  PCI_CXL_CAP_VIRAL     0x4000  /* CXL Viral Handling Support */
-#define PCI_CXL_CTRL           0x0c    /* CXL Control Register */
-#define  PCI_CXL_CTRL_CACHE    0x0001  /* CXL.cache Protocol Enable */
-#define  PCI_CXL_CTRL_IO       0x0002  /* CXL.io Protocol Enable */
-#define  PCI_CXL_CTRL_MEM      0x0004  /* CXL.mem Protocol Enable */
-#define  PCI_CXL_CTRL_CACHE_SF_COV(x)  (((x) & (0x1f << 3)) >> 3) /* Snoop Filter Coverage */
-#define  PCI_CXL_CTRL_CACHE_SF_GRAN(x) (((x) & (0x7 << 8)) >> 8) /* Snoop Filter Granularity */
-#define  PCI_CXL_CTRL_CACHE_CLN        0x0800  /* CXL.cache Performance Hint on Clean Evictions */
-#define  PCI_CXL_CTRL_VIRAL    0x4000  /* CXL Viral Handling Enable */
-#define PCI_CXL_STATUS         0x0e    /* CXL Status Register */
-#define  PCI_CXL_STATUS_VIRAL  0x4000  /* CXL Viral Handling Status */
+#define PCI_CXL_DEV_CAP                        0x0a    /* CXL Capability Register */
+#define  PCI_CXL_DEV_CAP_CACHE         0x0001  /* CXL.cache Protocol Support */
+#define  PCI_CXL_DEV_CAP_IO            0x0002  /* CXL.io Protocol Support */
+#define  PCI_CXL_DEV_CAP_MEM           0x0004  /* CXL.mem Protocol Support */
+#define  PCI_CXL_DEV_CAP_MEM_HWINIT    0x0008  /* CXL.mem Initializes with HW/FW Support */
+#define  PCI_CXL_DEV_CAP_HDM_CNT(x)    (((x) & (3 << 4)) >> 4) /* CXL Number of HDM ranges */
+#define  PCI_CXL_DEV_CAP_VIRAL         0x4000  /* CXL Viral Handling Support */
+#define PCI_CXL_DEV_CTRL               0x0c    /* CXL Control Register */
+#define  PCI_CXL_DEV_CTRL_CACHE                0x0001  /* CXL.cache Protocol Enable */
+#define  PCI_CXL_DEV_CTRL_IO           0x0002  /* CXL.io Protocol Enable */
+#define  PCI_CXL_DEV_CTRL_MEM          0x0004  /* CXL.mem Protocol Enable */
+#define  PCI_CXL_DEV_CTRL_CACHE_SF_COV(x) (((x) & (0x1f << 3)) >> 3) /* Snoop Filter Coverage */
+#define  PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(x) (((x) & (0x7 << 8)) >> 8) /* Snoop Filter Granularity */
+#define  PCI_CXL_DEV_CTRL_CACHE_CLN    0x0800  /* CXL.cache Performance Hint on Clean Evictions */
+#define  PCI_CXL_DEV_CTRL_VIRAL                0x4000  /* CXL Viral Handling Enable */
+#define PCI_CXL_DEV_STATUS             0x0e    /* CXL Status Register */
+#define  PCI_CXL_DEV_STATUS_VIRAL      0x4000  /* CXL Viral Handling Status */
 
 /* Access Control Services */
 #define PCI_ACS_CAP            0x04    /* ACS Capability Register */

diff --git a/ls-ecaps.c b/ls-ecaps.c
index 432d95a87cc360cdf7e69b23a0b9907becdf7009..d4636eb716c1513e53416f6813225bb9ff3fb8ec 100644 (file)
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -698,19 +698,19 @@ dvsec_cxl_device(struct device *d, int where, int rev)
   if (rev < 1)
     return;
 
-  w = get_conf_word(d, where + PCI_CXL_CAP);
+  w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
   printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n",
-    FLAG(w, PCI_CXL_CAP_CACHE), FLAG(w, PCI_CXL_CAP_IO), FLAG(w, PCI_CXL_CAP_MEM),
-    FLAG(w, PCI_CXL_CAP_MEM_HWINIT), PCI_CXL_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_CAP_VIRAL));
+    FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM),
+    FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL));
 
-  w = get_conf_word(d, where + PCI_CXL_CTRL);
+  w = get_conf_word(d, where + PCI_CXL_DEV_CTRL);
   printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n",
-    FLAG(w, PCI_CXL_CTRL_CACHE), FLAG(w, PCI_CXL_CTRL_IO), FLAG(w, PCI_CXL_CTRL_MEM),
-    PCI_CXL_CTRL_CACHE_SF_COV(w), PCI_CXL_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_CTRL_CACHE_CLN),
-    FLAG(w, PCI_CXL_CTRL_VIRAL));
+    FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
+    PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
+    FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
 
-  w = get_conf_word(d, where + PCI_CXL_STATUS);
-  printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_STATUS_VIRAL));
+  w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
+  printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
 }
 
 static void