lspci: Add support for CXL MLD DVSEC

Add MLD DVSEC decoding for CXL device accoring to DVSEC revision ID 0.
Decode Number of Logical Devices Supported.

Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>

diff --git a/lib/header.h b/lib/header.h
index 5dbd8ac2d8786839d3f4f104578e7fb8d948555f..84600b5e18ddefe0ecb7e99c58aa8327cf730281 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -1193,6 +1193,11 @@
 #define  PCI_CXL_FB_CTRL2_NOP_HINT          0x01    /* NOP Hint Enable */
 #define PCI_CXL_FB_PORT_STATUS2             0x1c    /* CXL Flex Bus Port Status2 Register */
 
+/* PCIe CXL Designated Vendor-Specific Capabilities for Multi-Logical Device */
+#define PCI_CXL_MLD_LEN     0x10
+#define PCI_CXL_MLD_NUM_LD  0xa
+#define PCI_CXL_MLD_MAX_LD  0x10
+
 /* Access Control Services */
 #define PCI_ACS_CAP            0x04    /* ACS Capability Register */
 #define PCI_ACS_CAP_VALID      0x0001  /* ACS Source Validation */

diff --git a/ls-ecaps.c b/ls-ecaps.c
index 32108cd32fc0c824b5e7706ca852d69d742931b2..b4e6a630ee05e2eb71f9b62986bd27ad9f2b1cbc 100644 (file)
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -1014,6 +1014,18 @@ dvsec_cxl_flex_bus(struct device *d, int where, int rev)
     }
 }
 
+static void
+dvsec_cxl_mld(struct device *d, int where)
+{
+  u16 w;
+
+  w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD);
+
+  /* Encodings greater than 16 are reserved */
+  if (w && w <= PCI_CXL_MLD_MAX_LD)
+    printf("\t\tNumLogDevs: %d\n", w);
+}
+
 static void
 cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
 {
@@ -1048,7 +1060,7 @@ cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
       dvsec_cxl_register_locator(d, where, len);
       break;
     case 9:
-      printf("\t\tMLD DVSEC\n");
+      dvsec_cxl_mld(d, where);
       break;
     default:
       printf("\t\tUnknown ID %04x\n", id);