The error bit is specified by the 2nd (zero indexed) bit
in the status register, so the respective bit value is 4 (PCI Base Spec
6.0.1). Let's fix that up.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
#define PCI_DOE_STS 0xC /* DOE Status Register */
#define PCI_DOE_STS_BUSY 0x1 /* DOE Busy */
#define PCI_DOE_STS_INT 0x2 /* DOE Interrupt Status */
-#define PCI_DOE_STS_ERROR 0x3 /* DOE Error */
+#define PCI_DOE_STS_ERROR 0x4 /* DOE Error */
#define PCI_DOE_STS_OBJECT_READY 0x80000000 /* Data Object Ready */
/*