lspci: fix "suprise" typo

This patch corrects the spelling of "surprise."

Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>

diff --git a/ls-caps.c b/ls-caps.c
index 0a19d4773e7be9d0dc05f718519f5246038722da..8b0f8204d4ec52dd230aaf56fb01d650d301014f 100644 (file)
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -752,7 +752,7 @@ static void cap_express_link(struct device *d, int where, int type)
        aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
        latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
        latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
-  printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
+  printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c\n",
        FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
        FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
        FLAG(t, PCI_EXP_LNKCAP_DLLA),

diff --git a/tests/cap-address-xlation b/tests/cap-address-xlation
index 75c02b9920707511bcf340d1a38535523b626ef6..493a63429e118d30e51a8d33256aa6f98403c4cb 100644 (file)
--- a/tests/cap-address-xlation
+++ b/tests/cap-address-xlation
@@ -20,7 +20,7 @@
                        MaxPayload 128 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited
-                       ClockPM- Suprise- LLActRep- BwNot-
+                       ClockPM- Surprise- LLActRep- BwNot-
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-

diff --git a/tests/cap-pcie-1 b/tests/cap-pcie-1
index f9621a026312454b167c7fccb1c13ac85513ef55..da5df1e6986293ff4f1c6eb997c388a1c18674a1 100644 (file)
--- a/tests/cap-pcie-1
+++ b/tests/cap-pcie-1
@@ -21,7 +21,7 @@
                        MaxPayload 128 bytes, MaxReadReq 128 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                LnkCap: Port #1, Speed 5GT/s, Width x4, ASPM unknown, Latency L0 <512ns, L1 <4us
-                       ClockPM- Suprise+ LLActRep+ BwNot+
+                       ClockPM- Surprise+ LLActRep+ BwNot+
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-

diff --git a/tests/cap-pcie-2 b/tests/cap-pcie-2
index 5221bd060f911f2cd83531e31b8c79601c8ade57..a50a3b964c7bb20252747015d18f61539785ff38 100644 (file)
--- a/tests/cap-pcie-2
+++ b/tests/cap-pcie-2
@@ -25,7 +25,7 @@
                        MaxPayload 256 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend-
                LnkCap: Port #2, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <4us, L1 <64us
-                       ClockPM- Suprise- LLActRep- BwNot-
+                       ClockPM- Surprise- LLActRep- BwNot-
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-