Add support for 32.0 GT/s header

diff --git a/lib/header.h b/lib/header.h
index 5ab606ff39f3d687585322a36cc741d1033c7855..57ef0ae8a31e9a7c521f7fc029981c2f52598a5f 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -254,6 +254,7 @@
 #define PCI_EXT_CAP_ID_LMR     0x27    /* Lane Margining at Receiver */
 #define PCI_EXT_CAP_ID_HIER_ID 0x28    /* Hierarchy ID */
 #define PCI_EXT_CAP_ID_NPEM    0x29    /* Native PCIe Enclosure Management */
 #define PCI_EXT_CAP_ID_LMR     0x27    /* Lane Margining at Receiver */
 #define PCI_EXT_CAP_ID_HIER_ID 0x28    /* Hierarchy ID */
 #define PCI_EXT_CAP_ID_NPEM    0x29    /* Native PCIe Enclosure Management */

+#define PCI_EXT_CAP_ID_32GT    0x2a    /* Physical Layer 32.0 GT/s */

 #define PCI_EXT_CAP_ID_DOE     0x2e    /* Data Object Exchange */
 
 /*** Definitions of capabilities ***/
 #define PCI_EXT_CAP_ID_DOE     0x2e    /* Data Object Exchange */
 
 /*** Definitions of capabilities ***/

diff --git a/ls-ecaps.c b/ls-ecaps.c
index 1bd1bf7b7418582b127b26d8cd3e047689f56533..6028607e82179beda0acf1110ada22bc1c9c7f19 100644 (file)
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -1556,6 +1556,9 @@ show_ext_caps(struct device *d, int type)
          case PCI_EXT_CAP_ID_NPEM:
            printf("Native PCIe Enclosure Management <?>\n");
            break;
          case PCI_EXT_CAP_ID_NPEM:
            printf("Native PCIe Enclosure Management <?>\n");
            break;

+      case PCI_EXT_CAP_ID_32GT:
+           printf("Physical Layer 32.0 GT/s <?>\n");
+        break;

          case PCI_EXT_CAP_ID_DOE:
            cap_doe(d, where);
            break;
          case PCI_EXT_CAP_ID_DOE:
            cap_doe(d, where);
            break;