PCIe r6.0, sec 7.9.26.4.2 "Link IDE Stream Status Register defines"
the link state as:
0000b Insecure
0010b Secure
The same definition applies to selective streams as well.
The existing code wrongly assumes "secure" is 0001b, fix that for both
link and selective streams.
While at this, add missing "Selective IDE for Configuration Requests Enable".
Also fix the base and limit parsing for the memory and RID ranges.
Fixes: 42fc4263ec0e ("ls-ecaps: Add decode support for IDE Extended Capability")
Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
#define PCI_IDE_SEL_CTL_TX_AGGR_PR(x) (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */
#define PCI_IDE_SEL_CTL_TX_AGGR_CPL(x) (((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */
#define PCI_IDE_SEL_CTL_PCRC_EN 0x100 /* PCRC Enable */
#define PCI_IDE_SEL_CTL_TX_AGGR_PR(x) (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */
#define PCI_IDE_SEL_CTL_TX_AGGR_CPL(x) (((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */
#define PCI_IDE_SEL_CTL_PCRC_EN 0x100 /* PCRC Enable */
+#define PCI_IDE_SEL_CTL_CFG_EN 0x200 /* Selective IDE for Configuration Requests Enable */
#define PCI_IDE_SEL_CTL_PART_ENC(x) (((x) >> 10) & 0xf) /* Partial Header Encryption Mode */
#define PCI_IDE_SEL_CTL_ALG(x) (((x) >> 14) & 0x1f) /* Selected Algorithm */
#define PCI_IDE_SEL_CTL_TC(x) (((x) >> 19) & 0x7) /* Traffic Class */
#define PCI_IDE_SEL_CTL_PART_ENC(x) (((x) >> 10) & 0xf) /* Partial Header Encryption Mode */
#define PCI_IDE_SEL_CTL_ALG(x) (((x) >> 14) & 0x1f) /* Selected Algorithm */
#define PCI_IDE_SEL_CTL_TC(x) (((x) >> 19) & 0x7) /* Traffic Class */
cap_ide(struct device *d, int where)
{
const char *hdr_enc_mode[] = { "no", "17:2", "25:2", "33:2", "41:2" };
cap_ide(struct device *d, int where)
{
const char *hdr_enc_mode[] = { "no", "17:2", "25:2", "33:2", "41:2" };
- const char *stream_state[] = { "insecure", "secure" };
+ const char *stream_state[] = { "insecure", "reserved", "secure" };
const char *aggr[] = { "-", "=2", "=4", "=8" };
u32 l, l2, linknum = 0, selnum = 0, addrnum, off, i, j;
char buf1[16], buf2[16], offs[16];
const char *aggr[] = { "-", "=2", "=4", "=8" };
u32 l, l2, linknum = 0, selnum = 0, addrnum, off, i, j;
char buf1[16], buf2[16], offs[16];
// Selective IDE Stream Control Register
l = get_conf_long(d, off);
// Selective IDE Stream Control Register
l = get_conf_long(d, off);
- printf("\t\t%sSelectiveIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d%s\n",
+ printf("\t\t%sSelectiveIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c CFG%c HdrEnc=%s Alg='%s' TC%d ID%d%s\n",
offstr(offs, off),
i,
FLAG(l, PCI_IDE_SEL_CTL_EN),
offstr(offs, off),
i,
FLAG(l, PCI_IDE_SEL_CTL_EN),
aggr[PCI_IDE_SEL_CTL_TX_AGGR_PR(l)],
aggr[PCI_IDE_SEL_CTL_TX_AGGR_CPL(l)],
FLAG(l, PCI_IDE_SEL_CTL_PCRC_EN),
aggr[PCI_IDE_SEL_CTL_TX_AGGR_PR(l)],
aggr[PCI_IDE_SEL_CTL_TX_AGGR_CPL(l)],
FLAG(l, PCI_IDE_SEL_CTL_PCRC_EN),
+ FLAG(l, PCI_IDE_SEL_CTL_CFG_EN),
TABLE(hdr_enc_mode, PCI_IDE_SEL_CTL_PART_ENC(l), buf1),
ide_alg(buf2, sizeof(buf2), PCI_IDE_SEL_CTL_ALG(l)),
PCI_IDE_SEL_CTL_TC(l),
TABLE(hdr_enc_mode, PCI_IDE_SEL_CTL_PART_ENC(l), buf1),
ide_alg(buf2, sizeof(buf2), PCI_IDE_SEL_CTL_ALG(l)),
PCI_IDE_SEL_CTL_TC(l),
l = get_conf_long(d, off);
limit = get_conf_long(d, off + 4);
l = get_conf_long(d, off);
limit = get_conf_long(d, off + 4);
+ limit <<= 32;
+ limit |= (PCI_IDE_SEL_ADDR_1_LIMIT_LOW(l) << 20) | 0xFFFFF;
base = get_conf_long(d, off + 8);
base = get_conf_long(d, off + 8);
+ base <<= 32;
+ base |= PCI_IDE_SEL_ADDR_1_BASE_LOW(l) << 20;
printf("\t\t%sSelectiveIDE#%d RID#%d: Valid%c Base=%lx Limit=%lx\n",
offstr(offs, off),
i,
j,
FLAG(l, PCI_IDE_SEL_ADDR_1_VALID),
printf("\t\t%sSelectiveIDE#%d RID#%d: Valid%c Base=%lx Limit=%lx\n",
offstr(offs, off),
i,
j,
FLAG(l, PCI_IDE_SEL_ADDR_1_VALID),
- (base << 32) | PCI_IDE_SEL_ADDR_1_BASE_LOW(l),
- (limit << 32) | PCI_IDE_SEL_ADDR_1_LIMIT_LOW(l));
IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ Alg='AES-GCM-256-96b' TCs=8 TeeLim+
IDECtl: FTEn-
SelectiveIDE#0 Cap: RID#=1
IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ Alg='AES-GCM-256-96b' TCs=8 TeeLim+
IDECtl: FTEn-
SelectiveIDE#0 Cap: RID#=1
- SelectiveIDE#0 Ctl: En- NPR- PR- CPL- PCRC- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0
- SelectiveIDE#0 Sta: insecure RecvChkFail-
- SelectiveIDE#0 RID: Valid- Base=0 Limit=0 SegBase=0
- SelectiveIDE#0 RID#0: Valid- Base=0 Limit=0
+ SelectiveIDE#0 Ctl: En+ NPR- PR- CPL- PCRC- CFG- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0 Default
+ SelectiveIDE#0 Sta: secure RecvChkFail-
+ SelectiveIDE#0 RID: Valid+ Base=0 Limit=ffff SegBase=0
+ SelectiveIDE#0 RID#0: Valid+ Base=0 Limit=ffffffffffffffff
Capabilities: [e00 v2] Data Object Exchange
DOECap: IntSup-
DOECtl: IntEn-
Capabilities: [e00 v2] Data Object Exchange
DOECap: IntSup-
DOECtl: IntEn-
810: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
820: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
830: 30 00 01 e0 42 e0 00 01 00 00 00 00 01 00 00 00
810: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
820: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
830: 30 00 01 e0 42 e0 00 01 00 00 00 00 01 00 00 00
-840: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-850: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+840: 01 00 40 00 02 00 00 00 00 ff ff 00 01 00 00 00
+850: 01 00 f0 ff ff ff ff ff 00 00 00 00 00 00 00 00
860: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
870: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
880: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
860: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
870: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
880: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00