UnDOSify

diff --git a/Inc/main.h b/Inc/main.h
index f1f81156c71b7d5765d7deb8735521a1e29ee70a..6683e3504ffff65a021cd1a0f1f69a15d1826e0d 100644 (file)
--- a/Inc/main.h
+++ b/Inc/main.h
@@ -1,111 +1,111 @@
-/**\r
-  ******************************************************************************\r
-  * @file           : main.h\r
-  * @brief          : Header for main.c file.\r
-  *                   This file contains the common defines of the application.\r
-  ******************************************************************************\r
-  ** This notice applies to any and all portions of this file\r
-  * that are not between comment pairs USER CODE BEGIN and\r
-  * USER CODE END. Other portions of this file, whether \r
-  * inserted by the user or by software development tools\r
-  * are owned by their respective copyright owners.\r
-  *\r
-  * COPYRIGHT(c) 2018 STMicroelectronics\r
-  *\r
-  * Redistribution and use in source and binary forms, with or without modification,\r
-  * are permitted provided that the following conditions are met:\r
-  *   1. Redistributions of source code must retain the above copyright notice,\r
-  *      this list of conditions and the following disclaimer.\r
-  *   2. Redistributions in binary form must reproduce the above copyright notice,\r
-  *      this list of conditions and the following disclaimer in the documentation\r
-  *      and/or other materials provided with the distribution.\r
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r
-  *      may be used to endorse or promote products derived from this software\r
-  *      without specific prior written permission.\r
-  *\r
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __MAIN_H__\r
-#define __MAIN_H__\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f0xx_ll_crs.h"\r
-#include "stm32f0xx_ll_rcc.h"\r
-#include "stm32f0xx_ll_bus.h"\r
-#include "stm32f0xx_ll_system.h"\r
-#include "stm32f0xx_ll_exti.h"\r
-#include "stm32f0xx_ll_cortex.h"\r
-#include "stm32f0xx_ll_utils.h"\r
-#include "stm32f0xx_ll_pwr.h"\r
-#include "stm32f0xx_ll_dma.h"\r
-#include "stm32f0xx_ll_usart.h"\r
-#include "stm32f0xx_ll_gpio.h"\r
-\r
-/* USER CODE BEGIN Includes */\r
-\r
-/* USER CODE END Includes */\r
-\r
-/* Private define ------------------------------------------------------------*/\r
-\r
-#define B1_Pin LL_GPIO_PIN_13\r
-#define B1_GPIO_Port GPIOC\r
-#define USART_TX_Pin LL_GPIO_PIN_2\r
-#define USART_TX_GPIO_Port GPIOA\r
-#define USART_RX_Pin LL_GPIO_PIN_3\r
-#define USART_RX_GPIO_Port GPIOA\r
-#define LD2_Pin LL_GPIO_PIN_5\r
-#define LD2_GPIO_Port GPIOA\r
-#define TMS_Pin LL_GPIO_PIN_13\r
-#define TMS_GPIO_Port GPIOA\r
-#define TCK_Pin LL_GPIO_PIN_14\r
-#define TCK_GPIO_Port GPIOA\r
-#ifndef NVIC_PRIORITYGROUP_0\r
-#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,\r
-                                                                 4 bits for subpriority */\r
-#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,\r
-                                                                 3 bits for subpriority */\r
-#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,\r
-                                                                 2 bits for subpriority */\r
-#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,\r
-                                                                 1 bit  for subpriority */\r
-#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,\r
-                                                                 0 bit  for subpriority */\r
-#endif\r
-\r
-/* ########################## Assert Selection ############################## */\r
-/**\r
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the \r
-  *        HAL drivers code\r
-  */\r
-/* #define USE_FULL_ASSERT    1U */\r
-\r
-/* USER CODE BEGIN Private defines */\r
-\r
-/* USER CODE END Private defines */\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-void _Error_Handler(char *, int);\r
-\r
-#define Error_Handler() _Error_Handler(__FILE__, __LINE__)\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __MAIN_H__ */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  ** This notice applies to any and all portions of this file
+  * that are not between comment pairs USER CODE BEGIN and
+  * USER CODE END. Other portions of this file, whether 
+  * inserted by the user or by software development tools
+  * are owned by their respective copyright owners.
+  *
+  * COPYRIGHT(c) 2018 STMicroelectronics
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H__
+#define __MAIN_H__
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_ll_crs.h"
+#include "stm32f0xx_ll_rcc.h"
+#include "stm32f0xx_ll_bus.h"
+#include "stm32f0xx_ll_system.h"
+#include "stm32f0xx_ll_exti.h"
+#include "stm32f0xx_ll_cortex.h"
+#include "stm32f0xx_ll_utils.h"
+#include "stm32f0xx_ll_pwr.h"
+#include "stm32f0xx_ll_dma.h"
+#include "stm32f0xx_ll_usart.h"
+#include "stm32f0xx_ll_gpio.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private define ------------------------------------------------------------*/
+
+#define B1_Pin LL_GPIO_PIN_13
+#define B1_GPIO_Port GPIOC
+#define USART_TX_Pin LL_GPIO_PIN_2
+#define USART_TX_GPIO_Port GPIOA
+#define USART_RX_Pin LL_GPIO_PIN_3
+#define USART_RX_GPIO_Port GPIOA
+#define LD2_Pin LL_GPIO_PIN_5
+#define LD2_GPIO_Port GPIOA
+#define TMS_Pin LL_GPIO_PIN_13
+#define TMS_GPIO_Port GPIOA
+#define TCK_Pin LL_GPIO_PIN_14
+#define TCK_GPIO_Port GPIOA
+#ifndef NVIC_PRIORITYGROUP_0
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+#endif
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+void _Error_Handler(char *, int);
+
+#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/Makefile b/Makefile
index 8d21bc88dcee33a6b57c5e74f2a0a4e9d2de83c6..048f2c7fa61f13a7b2d6b8be5b6101908eb7293d 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,195 +1,195 @@
-##########################################################################################################################\r
-# File automatically-generated by tool: [projectgenerator] version: [2.27.0] date: [Sat May 26 12:54:44 CEST 2018] \r
-##########################################################################################################################\r
-\r
-# ------------------------------------------------\r
-# Generic Makefile (based on gcc)\r
-#\r
-# ChangeLog :\r
-#      2017-02-10 - Several enhancements + project update mode\r
-#   2015-07-22 - first version\r
-# ------------------------------------------------\r
-\r
-######################################\r
-# target\r
-######################################\r
-TARGET = test\r
-\r
-\r
-######################################\r
-# building variables\r
-######################################\r
-# debug build?\r
-DEBUG = 1\r
-# optimization\r
-OPT = -Og\r
-\r
-\r
-#######################################\r
-# paths\r
-#######################################\r
-# source path\r
-SOURCES_DIR =  \\r
-Drivers/STM32F0xx_HAL_Driver \\r
-Application \\r
-Application/User/Src/stm32f0xx_it.c \\r
-Drivers/CMSIS \\r
-Application/User/Src \\r
-Application/User \\r
-Application/User/Src/main.c \\r
-Drivers\r
-\r
-# firmware library path\r
-PERIFLIB_PATH = \r
-\r
-# Build path\r
-BUILD_DIR = build\r
-\r
-######################################\r
-# source\r
-######################################\r
-# C sources\r
-C_SOURCES =  \\r
-Src/main.c \\r
-Src/main.c \\r
-/Src/system_stm32f0xx.c \\r
-Src/stm32f0xx_it.c \\r
-Src/stm32f0xx_it.c \\r
-/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c \\r
-/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_usart.c \\r
-/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c \\r
-/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c \\r
-/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c \\r
-/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c \\r
-/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_dma.c\r
-\r
-# ASM sources\r
-ASM_SOURCES =  \\r
-startup_stm32f030x8.s\r
-\r
-\r
-######################################\r
-# firmware library\r
-######################################\r
-PERIFLIB_SOURCES = \r
-\r
-\r
-#######################################\r
-# binaries\r
-#######################################\r
-BINPATH = \r
-PREFIX = arm-none-eabi-\r
-CC = $(BINPATH)/$(PREFIX)gcc\r
-AS = $(BINPATH)/$(PREFIX)gcc -x assembler-with-cpp\r
-CP = $(BINPATH)/$(PREFIX)objcopy\r
-AR = $(BINPATH)/$(PREFIX)ar\r
-SZ = $(BINPATH)/$(PREFIX)size\r
-HEX = $(CP) -O ihex\r
-BIN = $(CP) -O binary -S\r
- \r
-#######################################\r
-# CFLAGS\r
-#######################################\r
-# cpu\r
-CPU = -mcpu=cortex-m0\r
-\r
-# fpu\r
-# NONE for Cortex-M0/M0+/M3\r
-\r
-# float-abi\r
-\r
-\r
-# mcu\r
-MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)\r
-\r
-# macros for gcc\r
-# AS defines\r
-AS_DEFS = \r
-\r
-# C defines\r
-C_DEFS =  \\r
--DUSE_FULL_LL_DRIVER \\r
--DSTM32F030x8\r
-\r
-\r
-# AS includes\r
-AS_INCLUDES = \r
-\r
-# C includes\r
-C_INCLUDES =  \\r
--IInc \\r
--I/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Inc \\r
--I/aux/misc/stm/F0-package/Drivers/CMSIS/Device/ST/STM32F0xx/Include \\r
--I/aux/misc/stm/F0-package/Drivers/CMSIS/Include\r
-\r
-\r
-# compile gcc flags\r
-ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections\r
-\r
-CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections\r
-\r
-ifeq ($(DEBUG), 1)\r
-CFLAGS += -g -gdwarf-2\r
-endif\r
-\r
-\r
-# Generate dependency information\r
-CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)"\r
-\r
-\r
-#######################################\r
-# LDFLAGS\r
-#######################################\r
-# link script\r
-LDSCRIPT = STM32F030R8Tx_FLASH.ld\r
-\r
-# libraries\r
-LIBS = -lc -lm -lnosys \r
-LIBDIR = \r
-LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections\r
-\r
-# default action: build all\r
-all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin\r
-\r
-\r
-#######################################\r
-# build the application\r
-#######################################\r
-# list of objects\r
-OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))\r
-vpath %.c $(sort $(dir $(C_SOURCES)))\r
-# list of ASM program objects\r
-OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))\r
-vpath %.s $(sort $(dir $(ASM_SOURCES)))\r
-\r
-$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) \r
-       $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@\r
-\r
-$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)\r
-       $(AS) -c $(CFLAGS) $< -o $@\r
-\r
-$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile\r
-       $(CC) $(OBJECTS) $(LDFLAGS) -o $@\r
-       $(SZ) $@\r
-\r
-$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)\r
-       $(HEX) $< $@\r
-       \r
-$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)\r
-       $(BIN) $< $@    \r
-       \r
-$(BUILD_DIR):\r
-       mkdir $@                \r
-\r
-#######################################\r
-# clean up\r
-#######################################\r
-clean:\r
-       -rm -fR .dep $(BUILD_DIR)\r
-  \r
-#######################################\r
-# dependencies\r
-#######################################\r
--include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)\r
-\r
-# *** EOF ***\r
+##########################################################################################################################
+# File automatically-generated by tool: [projectgenerator] version: [2.27.0] date: [Sat May 26 12:54:44 CEST 2018] 
+##########################################################################################################################
+
+# ------------------------------------------------
+# Generic Makefile (based on gcc)
+#
+# ChangeLog :
+#      2017-02-10 - Several enhancements + project update mode
+#   2015-07-22 - first version
+# ------------------------------------------------
+
+######################################
+# target
+######################################
+TARGET = test
+
+
+######################################
+# building variables
+######################################
+# debug build?
+DEBUG = 1
+# optimization
+OPT = -Og
+
+
+#######################################
+# paths
+#######################################
+# source path
+SOURCES_DIR =  \
+Drivers/STM32F0xx_HAL_Driver \
+Application \
+Application/User/Src/stm32f0xx_it.c \
+Drivers/CMSIS \
+Application/User/Src \
+Application/User \
+Application/User/Src/main.c \
+Drivers
+
+# firmware library path
+PERIFLIB_PATH = 
+
+# Build path
+BUILD_DIR = build
+
+######################################
+# source
+######################################
+# C sources
+C_SOURCES =  \
+Src/main.c \
+Src/main.c \
+/Src/system_stm32f0xx.c \
+Src/stm32f0xx_it.c \
+Src/stm32f0xx_it.c \
+/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_exti.c \
+/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_usart.c \
+/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_gpio.c \
+/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_pwr.c \
+/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_utils.c \
+/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_rcc.c \
+/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_dma.c
+
+# ASM sources
+ASM_SOURCES =  \
+startup_stm32f030x8.s
+
+
+######################################
+# firmware library
+######################################
+PERIFLIB_SOURCES = 
+
+
+#######################################
+# binaries
+#######################################
+BINPATH = 
+PREFIX = arm-none-eabi-
+CC = $(BINPATH)/$(PREFIX)gcc
+AS = $(BINPATH)/$(PREFIX)gcc -x assembler-with-cpp
+CP = $(BINPATH)/$(PREFIX)objcopy
+AR = $(BINPATH)/$(PREFIX)ar
+SZ = $(BINPATH)/$(PREFIX)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary -S
+ 
+#######################################
+# CFLAGS
+#######################################
+# cpu
+CPU = -mcpu=cortex-m0
+
+# fpu
+# NONE for Cortex-M0/M0+/M3
+
+# float-abi
+
+
+# mcu
+MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
+
+# macros for gcc
+# AS defines
+AS_DEFS = 
+
+# C defines
+C_DEFS =  \
+-DUSE_FULL_LL_DRIVER \
+-DSTM32F030x8
+
+
+# AS includes
+AS_INCLUDES = 
+
+# C includes
+C_INCLUDES =  \
+-IInc \
+-I/aux/misc/stm/F0-package/Drivers/STM32F0xx_HAL_Driver/Inc \
+-I/aux/misc/stm/F0-package/Drivers/CMSIS/Device/ST/STM32F0xx/Include \
+-I/aux/misc/stm/F0-package/Drivers/CMSIS/Include
+
+
+# compile gcc flags
+ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
+
+CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
+
+ifeq ($(DEBUG), 1)
+CFLAGS += -g -gdwarf-2
+endif
+
+
+# Generate dependency information
+CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)"
+
+
+#######################################
+# LDFLAGS
+#######################################
+# link script
+LDSCRIPT = STM32F030R8Tx_FLASH.ld
+
+# libraries
+LIBS = -lc -lm -lnosys 
+LIBDIR = 
+LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
+
+# default action: build all
+all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
+
+
+#######################################
+# build the application
+#######################################
+# list of objects
+OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
+vpath %.c $(sort $(dir $(C_SOURCES)))
+# list of ASM program objects
+OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
+vpath %.s $(sort $(dir $(ASM_SOURCES)))
+
+$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) 
+       $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
+
+$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
+       $(AS) -c $(CFLAGS) $< -o $@
+
+$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
+       $(CC) $(OBJECTS) $(LDFLAGS) -o $@
+       $(SZ) $@
+
+$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
+       $(HEX) $< $@
+       
+$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
+       $(BIN) $< $@    
+       
+$(BUILD_DIR):
+       mkdir $@                
+
+#######################################
+# clean up
+#######################################
+clean:
+       -rm -fR .dep $(BUILD_DIR)
+  
+#######################################
+# dependencies
+#######################################
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# *** EOF ***

diff --git a/STM32F030R8Tx_FLASH.ld b/STM32F030R8Tx_FLASH.ld
index 6ab4965eb34128f0f874e589b2a52cf0d2920ffd..b2e3eb9cd58554ed6ce646f6999a28c6bc69662c 100644 (file)
--- a/STM32F030R8Tx_FLASH.ld
+++ b/STM32F030R8Tx_FLASH.ld
@@ -1,169 +1,169 @@
-/*\r
-*****************************************************************************\r
-**\r
-\r
-**  File        : LinkerScript.ld\r
-**\r
-**  Abstract    : Linker script for STM32F030R8Tx Device with\r
-**                64KByte FLASH, 8KByte RAM\r
-**\r
-**                Set heap size, stack size and stack location according\r
-**                to application requirements.\r
-**\r
-**                Set memory bank area and size if external memory is used.\r
-**\r
-**  Target      : STMicroelectronics STM32\r
-**\r
-**\r
-**  Distribution: The file is distributed as is, without any warranty\r
-**                of any kind.\r
-**\r
-**  (c)Copyright Ac6.\r
-**  You may use this file as-is or modify it according to the needs of your\r
-**  project. Distribution of this file (unmodified or modified) is not\r
-**  permitted. Ac6 permit registered System Workbench for MCU users the\r
-**  rights to distribute the assembled, compiled & linked contents of this\r
-**  file as part of an application binary file, provided that it is built\r
-**  using the System Workbench for MCU toolchain.\r
-**\r
-*****************************************************************************\r
-*/\r
-\r
-/* Entry Point */\r
-ENTRY(Reset_Handler)\r
-\r
-/* Highest address of the user mode stack */\r
-_estack = 0x20002000;    /* end of RAM */\r
-/* Generate a link error if heap and stack don't fit into RAM */\r
-_Min_Heap_Size = 0x200;      /* required amount of heap  */\r
-_Min_Stack_Size = 0x400; /* required amount of stack */\r
-\r
-/* Specify the memory areas */\r
-MEMORY\r
-{\r
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 8K\r
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 64K\r
-}\r
-\r
-/* Define output sections */\r
-SECTIONS\r
-{\r
-  /* The startup code goes first into FLASH */\r
-  .isr_vector :\r
-  {\r
-    . = ALIGN(4);\r
-    KEEP(*(.isr_vector)) /* Startup code */\r
-    . = ALIGN(4);\r
-  } >FLASH\r
-\r
-  /* The program code and other data goes into FLASH */\r
-  .text :\r
-  {\r
-    . = ALIGN(4);\r
-    *(.text)           /* .text sections (code) */\r
-    *(.text*)          /* .text* sections (code) */\r
-    *(.glue_7)         /* glue arm to thumb code */\r
-    *(.glue_7t)        /* glue thumb to arm code */\r
-    *(.eh_frame)\r
-\r
-    KEEP (*(.init))\r
-    KEEP (*(.fini))\r
-\r
-    . = ALIGN(4);\r
-    _etext = .;        /* define a global symbols at end of code */\r
-  } >FLASH\r
-\r
-  /* Constant data goes into FLASH */\r
-  .rodata :\r
-  {\r
-    . = ALIGN(4);\r
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */\r
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\r
-    . = ALIGN(4);\r
-  } >FLASH\r
-\r
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\r
-  .ARM : {\r
-    __exidx_start = .;\r
-    *(.ARM.exidx*)\r
-    __exidx_end = .;\r
-  } >FLASH\r
-\r
-  .preinit_array     :\r
-  {\r
-    PROVIDE_HIDDEN (__preinit_array_start = .);\r
-    KEEP (*(.preinit_array*))\r
-    PROVIDE_HIDDEN (__preinit_array_end = .);\r
-  } >FLASH\r
-  .init_array :\r
-  {\r
-    PROVIDE_HIDDEN (__init_array_start = .);\r
-    KEEP (*(SORT(.init_array.*)))\r
-    KEEP (*(.init_array*))\r
-    PROVIDE_HIDDEN (__init_array_end = .);\r
-  } >FLASH\r
-  .fini_array :\r
-  {\r
-    PROVIDE_HIDDEN (__fini_array_start = .);\r
-    KEEP (*(SORT(.fini_array.*)))\r
-    KEEP (*(.fini_array*))\r
-    PROVIDE_HIDDEN (__fini_array_end = .);\r
-  } >FLASH\r
-\r
-  /* used by the startup to initialize data */\r
-  _sidata = LOADADDR(.data);\r
-\r
-  /* Initialized data sections goes into RAM, load LMA copy after code */\r
-  .data : \r
-  {\r
-    . = ALIGN(4);\r
-    _sdata = .;        /* create a global symbol at data start */\r
-    *(.data)           /* .data sections */\r
-    *(.data*)          /* .data* sections */\r
-\r
-    . = ALIGN(4);\r
-    _edata = .;        /* define a global symbol at data end */\r
-  } >RAM AT> FLASH\r
-\r
-  \r
-  /* Uninitialized data section */\r
-  . = ALIGN(4);\r
-  .bss :\r
-  {\r
-    /* This is used by the startup in order to initialize the .bss secion */\r
-    _sbss = .;         /* define a global symbol at bss start */\r
-    __bss_start__ = _sbss;\r
-    *(.bss)\r
-    *(.bss*)\r
-    *(COMMON)\r
-\r
-    . = ALIGN(4);\r
-    _ebss = .;         /* define a global symbol at bss end */\r
-    __bss_end__ = _ebss;\r
-  } >RAM\r
-\r
-  /* User_heap_stack section, used to check that there is enough RAM left */\r
-  ._user_heap_stack :\r
-  {\r
-    . = ALIGN(8);\r
-    PROVIDE ( end = . );\r
-    PROVIDE ( _end = . );\r
-    . = . + _Min_Heap_Size;\r
-    . = . + _Min_Stack_Size;\r
-    . = ALIGN(8);\r
-  } >RAM\r
-\r
-  \r
-\r
-  /* Remove information from the standard libraries */\r
-  /DISCARD/ :\r
-  {\r
-    libc.a ( * )\r
-    libm.a ( * )\r
-    libgcc.a ( * )\r
-  }\r
-\r
-  .ARM.attributes 0 : { *(.ARM.attributes) }\r
-}\r
-\r
-\r
+/*
+*****************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Abstract    : Linker script for STM32F030R8Tx Device with
+**                64KByte FLASH, 8KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+**  (c)Copyright Ac6.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Ac6 permit registered System Workbench for MCU users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the System Workbench for MCU toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20002000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 8K
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 64K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+

diff --git a/Src/main.c b/Src/main.c
index 927aabf447c53550ff68d464e2854fbe8aeec0a2..02220adda978003e7bc1dd0548c9177cb37f073a 100644 (file)
--- a/Src/main.c
+++ b/Src/main.c
@@ -1,326 +1,326 @@
-\r
-/**\r
-  ******************************************************************************\r
-  * @file           : main.c\r
-  * @brief          : Main program body\r
-  ******************************************************************************\r
-  ** This notice applies to any and all portions of this file\r
-  * that are not between comment pairs USER CODE BEGIN and\r
-  * USER CODE END. Other portions of this file, whether \r
-  * inserted by the user or by software development tools\r
-  * are owned by their respective copyright owners.\r
-  *\r
-  * COPYRIGHT(c) 2018 STMicroelectronics\r
-  *\r
-  * Redistribution and use in source and binary forms, with or without modification,\r
-  * are permitted provided that the following conditions are met:\r
-  *   1. Redistributions of source code must retain the above copyright notice,\r
-  *      this list of conditions and the following disclaimer.\r
-  *   2. Redistributions in binary form must reproduce the above copyright notice,\r
-  *      this list of conditions and the following disclaimer in the documentation\r
-  *      and/or other materials provided with the distribution.\r
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r
-  *      may be used to endorse or promote products derived from this software\r
-  *      without specific prior written permission.\r
-  *\r
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
-  *\r
-  ******************************************************************************\r
-  */\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "main.h"\r
-\r
-/* USER CODE BEGIN Includes */\r
-\r
-/* USER CODE END Includes */\r
-\r
-/* Private variables ---------------------------------------------------------*/\r
-\r
-/* USER CODE BEGIN PV */\r
-/* Private variables ---------------------------------------------------------*/\r
-\r
-/* USER CODE END PV */\r
-\r
-/* Private function prototypes -----------------------------------------------*/\r
-static void LL_Init(void);\r
-void SystemClock_Config(void);\r
-static void MX_GPIO_Init(void);\r
-static void MX_USART2_UART_Init(void);\r
-\r
-/* USER CODE BEGIN PFP */\r
-/* Private function prototypes -----------------------------------------------*/\r
-\r
-/* USER CODE END PFP */\r
-\r
-/* USER CODE BEGIN 0 */\r
-\r
-/* USER CODE END 0 */\r
-\r
-/**\r
-  * @brief  The application entry point.\r
-  *\r
-  * @retval None\r
-  */\r
-int main(void)\r
-{\r
-  /* USER CODE BEGIN 1 */\r
-\r
-  /* USER CODE END 1 */\r
-\r
-  /* MCU Configuration----------------------------------------------------------*/\r
-\r
-  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */\r
-  LL_Init();\r
-\r
-  /* USER CODE BEGIN Init */\r
-\r
-  /* USER CODE END Init */\r
-\r
-  /* Configure the system clock */\r
-  SystemClock_Config();\r
-\r
-  /* USER CODE BEGIN SysInit */\r
-\r
-  /* USER CODE END SysInit */\r
-\r
-  /* Initialize all configured peripherals */\r
-  MX_GPIO_Init();\r
-  MX_USART2_UART_Init();\r
-  /* USER CODE BEGIN 2 */\r
-\r
-  /* USER CODE END 2 */\r
-\r
-  /* Infinite loop */\r
-  /* USER CODE BEGIN WHILE */\r
-  while (1)\r
-  {\r
-\r
-  /* USER CODE END WHILE */\r
-\r
-  /* USER CODE BEGIN 3 */\r
-\r
-  }\r
-  /* USER CODE END 3 */\r
-\r
-}\r
-\r
-static void LL_Init(void)\r
-{\r
-  \r
-\r
-  LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);\r
-\r
-  /* System interrupt init*/\r
-  /* SVC_IRQn interrupt configuration */\r
-  NVIC_SetPriority(SVC_IRQn, 0);\r
-  /* PendSV_IRQn interrupt configuration */\r
-  NVIC_SetPriority(PendSV_IRQn, 0);\r
-  /* SysTick_IRQn interrupt configuration */\r
-  NVIC_SetPriority(SysTick_IRQn, 0);\r
-\r
-}\r
-\r
-/**\r
-  * @brief System Clock Configuration\r
-  * @retval None\r
-  */\r
-void SystemClock_Config(void)\r
-{\r
-\r
-  LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);\r
-\r
-  if(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_1)\r
-  {\r
-  Error_Handler();  \r
-  }\r
-  LL_RCC_HSI_Enable();\r
-\r
-   /* Wait till HSI is ready */\r
-  while(LL_RCC_HSI_IsReady() != 1)\r
-  {\r
-    \r
-  }\r
-  LL_RCC_HSI_SetCalibTrimming(16);\r
-\r
-  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, LL_RCC_PLL_MUL_8);\r
-\r
-  LL_RCC_PLL_Enable();\r
-\r
-   /* Wait till PLL is ready */\r
-  while(LL_RCC_PLL_IsReady() != 1)\r
-  {\r
-    \r
-  }\r
-  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);\r
-\r
-  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);\r
-\r
-  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);\r
-\r
-   /* Wait till System clock is ready */\r
-  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)\r
-  {\r
-  \r
-  }\r
-  LL_Init1msTick(32000000);\r
-\r
-  LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK);\r
-\r
-  LL_SetSystemCoreClock(32000000);\r
-\r
-  /* SysTick_IRQn interrupt configuration */\r
-  NVIC_SetPriority(SysTick_IRQn, 0);\r
-}\r
-\r
-/* USART2 init function */\r
-static void MX_USART2_UART_Init(void)\r
-{\r
-\r
-  LL_USART_InitTypeDef USART_InitStruct;\r
-\r
-  LL_GPIO_InitTypeDef GPIO_InitStruct;\r
-\r
-  /* Peripheral clock enable */\r
-  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2);\r
-  \r
-  /**USART2 GPIO Configuration  \r
-  PA2   ------> USART2_TX\r
-  PA3   ------> USART2_RX \r
-  */\r
-  GPIO_InitStruct.Pin = USART_TX_Pin;\r
-  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;\r
-  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;\r
-  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;\r
-  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;\r
-  GPIO_InitStruct.Alternate = LL_GPIO_AF_1;\r
-  LL_GPIO_Init(USART_TX_GPIO_Port, &GPIO_InitStruct);\r
-\r
-  GPIO_InitStruct.Pin = USART_RX_Pin;\r
-  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;\r
-  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;\r
-  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;\r
-  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;\r
-  GPIO_InitStruct.Alternate = LL_GPIO_AF_1;\r
-  LL_GPIO_Init(USART_RX_GPIO_Port, &GPIO_InitStruct);\r
-\r
-  USART_InitStruct.BaudRate = 38400;\r
-  USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;\r
-  USART_InitStruct.StopBits = LL_USART_STOPBITS_1;\r
-  USART_InitStruct.Parity = LL_USART_PARITY_NONE;\r
-  USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;\r
-  USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;\r
-  USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;\r
-  LL_USART_Init(USART2, &USART_InitStruct);\r
-\r
-  LL_USART_DisableIT_CTS(USART2);\r
-\r
-  LL_USART_DisableOverrunDetect(USART2);\r
-\r
-  LL_USART_ConfigAsyncMode(USART2);\r
-\r
-  LL_USART_Enable(USART2);\r
-\r
-}\r
-\r
-/** Configure pins as \r
-        * Analog \r
-        * Input \r
-        * Output\r
-        * EVENT_OUT\r
-        * EXTI\r
-*/\r
-static void MX_GPIO_Init(void)\r
-{\r
-\r
-  LL_EXTI_InitTypeDef EXTI_InitStruct;\r
-  LL_GPIO_InitTypeDef GPIO_InitStruct;\r
-\r
-  /* GPIO Ports Clock Enable */\r
-  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOC);\r
-  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF);\r
-  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);\r
-\r
-  /**/\r
-  LL_GPIO_ResetOutputPin(LD2_GPIO_Port, LD2_Pin);\r
-\r
-  /**/\r
-  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTC, LL_SYSCFG_EXTI_LINE13);\r
-\r
-  /**/\r
-  LL_GPIO_SetPinPull(B1_GPIO_Port, B1_Pin, LL_GPIO_PULL_NO);\r
-\r
-  /**/\r
-  LL_GPIO_SetPinMode(B1_GPIO_Port, B1_Pin, LL_GPIO_MODE_INPUT);\r
-\r
-  /**/\r
-  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_13;\r
-  EXTI_InitStruct.LineCommand = ENABLE;\r
-  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;\r
-  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;\r
-  LL_EXTI_Init(&EXTI_InitStruct);\r
-\r
-  /**/\r
-  GPIO_InitStruct.Pin = LD2_Pin;\r
-  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;\r
-  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;\r
-  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;\r
-  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;\r
-  LL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);\r
-\r
-}\r
-\r
-/* USER CODE BEGIN 4 */\r
-\r
-/* USER CODE END 4 */\r
-\r
-/**\r
-  * @brief  This function is executed in case of error occurrence.\r
-  * @param  file: The file name as string.\r
-  * @param  line: The line in file as a number.\r
-  * @retval None\r
-  */\r
-void _Error_Handler(char *file, int line)\r
-{\r
-  /* USER CODE BEGIN Error_Handler_Debug */\r
-  /* User can add his own implementation to report the HAL error return state */\r
-  while(1)\r
-  {\r
-  }\r
-  /* USER CODE END Error_Handler_Debug */\r
-}\r
-\r
-#ifdef  USE_FULL_ASSERT\r
-/**\r
-  * @brief  Reports the name of the source file and the source line number\r
-  *         where the assert_param error has occurred.\r
-  * @param  file: pointer to the source file name\r
-  * @param  line: assert_param error line source number\r
-  * @retval None\r
-  */\r
-void assert_failed(uint8_t* file, uint32_t line)\r
-{ \r
-  /* USER CODE BEGIN 6 */\r
-  /* User can add his own implementation to report the file name and line number,\r
-     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */\r
-  /* USER CODE END 6 */\r
-}\r
-#endif /* USE_FULL_ASSERT */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  ** This notice applies to any and all portions of this file
+  * that are not between comment pairs USER CODE BEGIN and
+  * USER CODE END. Other portions of this file, whether 
+  * inserted by the user or by software development tools
+  * are owned by their respective copyright owners.
+  *
+  * COPYRIGHT(c) 2018 STMicroelectronics
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+static void LL_Init(void);
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART2_UART_Init(void);
+
+/* USER CODE BEGIN PFP */
+/* Private function prototypes -----------------------------------------------*/
+
+/* USER CODE END PFP */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  *
+  * @retval None
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration----------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  LL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USART2_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+
+  /* USER CODE END WHILE */
+
+  /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+
+}
+
+static void LL_Init(void)
+{
+  
+
+  LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
+
+  /* System interrupt init*/
+  /* SVC_IRQn interrupt configuration */
+  NVIC_SetPriority(SVC_IRQn, 0);
+  /* PendSV_IRQn interrupt configuration */
+  NVIC_SetPriority(PendSV_IRQn, 0);
+  /* SysTick_IRQn interrupt configuration */
+  NVIC_SetPriority(SysTick_IRQn, 0);
+
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+
+  LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
+
+  if(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_1)
+  {
+  Error_Handler();  
+  }
+  LL_RCC_HSI_Enable();
+
+   /* Wait till HSI is ready */
+  while(LL_RCC_HSI_IsReady() != 1)
+  {
+    
+  }
+  LL_RCC_HSI_SetCalibTrimming(16);
+
+  LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, LL_RCC_PLL_MUL_8);
+
+  LL_RCC_PLL_Enable();
+
+   /* Wait till PLL is ready */
+  while(LL_RCC_PLL_IsReady() != 1)
+  {
+    
+  }
+  LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+
+  LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+
+  LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+
+   /* Wait till System clock is ready */
+  while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+  {
+  
+  }
+  LL_Init1msTick(32000000);
+
+  LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK);
+
+  LL_SetSystemCoreClock(32000000);
+
+  /* SysTick_IRQn interrupt configuration */
+  NVIC_SetPriority(SysTick_IRQn, 0);
+}
+
+/* USART2 init function */
+static void MX_USART2_UART_Init(void)
+{
+
+  LL_USART_InitTypeDef USART_InitStruct;
+
+  LL_GPIO_InitTypeDef GPIO_InitStruct;
+
+  /* Peripheral clock enable */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2);
+  
+  /**USART2 GPIO Configuration  
+  PA2   ------> USART2_TX
+  PA3   ------> USART2_RX 
+  */
+  GPIO_InitStruct.Pin = USART_TX_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_1;
+  LL_GPIO_Init(USART_TX_GPIO_Port, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = USART_RX_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  GPIO_InitStruct.Alternate = LL_GPIO_AF_1;
+  LL_GPIO_Init(USART_RX_GPIO_Port, &GPIO_InitStruct);
+
+  USART_InitStruct.BaudRate = 38400;
+  USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
+  USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
+  USART_InitStruct.Parity = LL_USART_PARITY_NONE;
+  USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
+  USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+  USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
+  LL_USART_Init(USART2, &USART_InitStruct);
+
+  LL_USART_DisableIT_CTS(USART2);
+
+  LL_USART_DisableOverrunDetect(USART2);
+
+  LL_USART_ConfigAsyncMode(USART2);
+
+  LL_USART_Enable(USART2);
+
+}
+
+/** Configure pins as 
+        * Analog 
+        * Input 
+        * Output
+        * EVENT_OUT
+        * EXTI
+*/
+static void MX_GPIO_Init(void)
+{
+
+  LL_EXTI_InitTypeDef EXTI_InitStruct;
+  LL_GPIO_InitTypeDef GPIO_InitStruct;
+
+  /* GPIO Ports Clock Enable */
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOC);
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF);
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);
+
+  /**/
+  LL_GPIO_ResetOutputPin(LD2_GPIO_Port, LD2_Pin);
+
+  /**/
+  LL_SYSCFG_SetEXTISource(LL_SYSCFG_EXTI_PORTC, LL_SYSCFG_EXTI_LINE13);
+
+  /**/
+  LL_GPIO_SetPinPull(B1_GPIO_Port, B1_Pin, LL_GPIO_PULL_NO);
+
+  /**/
+  LL_GPIO_SetPinMode(B1_GPIO_Port, B1_Pin, LL_GPIO_MODE_INPUT);
+
+  /**/
+  EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_13;
+  EXTI_InitStruct.LineCommand = ENABLE;
+  EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
+  EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_FALLING;
+  LL_EXTI_Init(&EXTI_InitStruct);
+
+  /**/
+  GPIO_InitStruct.Pin = LD2_Pin;
+  GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+  GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+  LL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @param  file: The file name as string.
+  * @param  line: The line in file as a number.
+  * @retval None
+  */
+void _Error_Handler(char *file, int line)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  while(1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/Src/stm32f0xx_it.c b/Src/stm32f0xx_it.c
index 18fd60ca90c43556b401dacf0037f75c8614eb5f..73f417117f5bbbf32b636296242f40ee7064a935 100644 (file)
--- a/Src/stm32f0xx_it.c
+++ b/Src/stm32f0xx_it.c
@@ -1,71 +1,71 @@
-/**\r
-  ******************************************************************************\r
-  * @file    stm32f0xx_it.c\r
-  * @brief   Interrupt Service Routines.\r
-  ******************************************************************************\r
-  *\r
-  * COPYRIGHT(c) 2018 STMicroelectronics\r
-  *\r
-  * Redistribution and use in source and binary forms, with or without modification,\r
-  * are permitted provided that the following conditions are met:\r
-  *   1. Redistributions of source code must retain the above copyright notice,\r
-  *      this list of conditions and the following disclaimer.\r
-  *   2. Redistributions in binary form must reproduce the above copyright notice,\r
-  *      this list of conditions and the following disclaimer in the documentation\r
-  *      and/or other materials provided with the distribution.\r
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r
-  *      may be used to endorse or promote products derived from this software\r
-  *      without specific prior written permission.\r
-  *\r
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
-  *\r
-  ******************************************************************************\r
-  */\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f0xx.h"\r
-#include "stm32f0xx_it.h"\r
-\r
-/* USER CODE BEGIN 0 */\r
-\r
-/* USER CODE END 0 */\r
-\r
-/* External variables --------------------------------------------------------*/\r
-\r
-/******************************************************************************/\r
-/*            Cortex-M0 Processor Interruption and Exception Handlers         */ \r
-/******************************************************************************/\r
-\r
-/**\r
-* @brief This function handles System tick timer.\r
-*/\r
-void SysTick_Handler(void)\r
-{\r
-  /* USER CODE BEGIN SysTick_IRQn 0 */\r
-\r
-  /* USER CODE END SysTick_IRQn 0 */\r
-  \r
-  /* USER CODE BEGIN SysTick_IRQn 1 */\r
-\r
-  /* USER CODE END SysTick_IRQn 1 */\r
-}\r
-\r
-/******************************************************************************/\r
-/* STM32F0xx Peripheral Interrupt Handlers                                    */\r
-/* Add here the Interrupt Handlers for the used peripherals.                  */\r
-/* For the available peripheral interrupt handler names,                      */\r
-/* please refer to the startup file (startup_stm32f0xx.s).                    */\r
-/******************************************************************************/\r
-\r
-/* USER CODE BEGIN 1 */\r
-\r
-/* USER CODE END 1 */\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+/**
+  ******************************************************************************
+  * @file    stm32f0xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  *
+  * COPYRIGHT(c) 2018 STMicroelectronics
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx.h"
+#include "stm32f0xx_it.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M0 Processor Interruption and Exception Handlers         */ 
+/******************************************************************************/
+
+/**
+* @brief This function handles System tick timer.
+*/
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F0xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32f0xx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/Src/system_stm32f0xx.c b/Src/system_stm32f0xx.c
index 36b46525297170296ee24e8ea3075a6761a88d74..410809c2b80f261dc453123388058b532c9a9e74 100644 (file)
--- a/Src/system_stm32f0xx.c
+++ b/Src/system_stm32f0xx.c
@@ -1,333 +1,333 @@
-/**\r
-  ******************************************************************************\r
-  * @file    system_stm32f0xx.c\r
-  * @author  MCD Application Team\r
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.\r
-  *\r
-  * 1. This file provides two functions and one global variable to be called from\r
-  *    user application:\r
-  *      - SystemInit(): This function is called at startup just after reset and \r
-  *                      before branch to main program. This call is made inside\r
-  *                      the "startup_stm32f0xx.s" file.\r
-  *\r
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\r
-  *                                  by the user application to setup the SysTick\r
-  *                                  timer or configure other parameters.\r
-  *\r
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\r
-  *                                 be called whenever the core clock is changed\r
-  *                                 during program execution.\r
-  *\r
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.\r
-  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to\r
-  *    configure the system clock before to branch to main program.\r
-  *\r
-  * 3. This file configures the system clock as follows:\r
-  *=============================================================================\r
-  *                         Supported STM32F0xx device\r
-  *-----------------------------------------------------------------------------\r
-  *        System Clock source                    | HSI\r
-  *-----------------------------------------------------------------------------\r
-  *        SYSCLK(Hz)                             | 8000000\r
-  *-----------------------------------------------------------------------------\r
-  *        HCLK(Hz)                               | 8000000\r
-  *-----------------------------------------------------------------------------\r
-  *        AHB Prescaler                          | 1\r
-  *-----------------------------------------------------------------------------\r
-  *        APB1 Prescaler                         | 1\r
-  *-----------------------------------------------------------------------------\r
-  *=============================================================================\r
-  ******************************************************************************\r
-  * @attention\r
-  *\r
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\r
-  *\r
-  * Redistribution and use in source and binary forms, with or without modification,\r
-  * are permitted provided that the following conditions are met:\r
-  *   1. Redistributions of source code must retain the above copyright notice,\r
-  *      this list of conditions and the following disclaimer.\r
-  *   2. Redistributions in binary form must reproduce the above copyright notice,\r
-  *      this list of conditions and the following disclaimer in the documentation\r
-  *      and/or other materials provided with the distribution.\r
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r
-  *      may be used to endorse or promote products derived from this software\r
-  *      without specific prior written permission.\r
-  *\r
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-/** @addtogroup CMSIS\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup stm32f0xx_system\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup STM32F0xx_System_Private_Includes\r
-  * @{\r
-  */\r
-\r
-#include "stm32f0xx.h"\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F0xx_System_Private_Defines\r
-  * @{\r
-  */\r
-#if !defined  (HSE_VALUE) \r
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.\r
-                                                This value can be provided and adapted by the user application. */\r
-#endif /* HSE_VALUE */\r
-\r
-#if !defined  (HSI_VALUE)\r
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.\r
-                                                This value can be provided and adapted by the user application. */\r
-#endif /* HSI_VALUE */\r
-\r
-#if !defined (HSI48_VALUE)\r
-#define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.\r
-                                                 This value can be provided and adapted by the user application. */\r
-#endif /* HSI48_VALUE */\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F0xx_System_Private_Macros\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F0xx_System_Private_Variables\r
-  * @{\r
-  */\r
-  /* This variable is updated in three ways:\r
-      1) by calling CMSIS function SystemCoreClockUpdate()\r
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\r
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\r
-         Note: If you use this function to configure the system clock there is no need to\r
-               call the 2 first functions listed above, since SystemCoreClock variable is \r
-               updated automatically.\r
-  */\r
-uint32_t SystemCoreClock = 8000000;\r
-\r
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F0xx_System_Private_Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Setup the microcontroller system.\r
-  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-void SystemInit(void)\r
-{\r
-  /* Reset the RCC clock configuration to the default reset state ------------*/\r
-  /* Set HSION bit */\r
-  RCC->CR |= (uint32_t)0x00000001U;\r
-\r
-#if defined (STM32F051x8) || defined (STM32F058x8)\r
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */\r
-  RCC->CFGR &= (uint32_t)0xF8FFB80CU;\r
-#else\r
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */\r
-  RCC->CFGR &= (uint32_t)0x08FFB80CU;\r
-#endif /* STM32F051x8 or STM32F058x8 */\r
-  \r
-  /* Reset HSEON, CSSON and PLLON bits */\r
-  RCC->CR &= (uint32_t)0xFEF6FFFFU;\r
-\r
-  /* Reset HSEBYP bit */\r
-  RCC->CR &= (uint32_t)0xFFFBFFFFU;\r
-\r
-  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */\r
-  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;\r
-\r
-  /* Reset PREDIV[3:0] bits */\r
-  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;\r
-\r
-#if defined (STM32F072xB) || defined (STM32F078xx)\r
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */\r
-  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;\r
-#elif defined (STM32F071xB)\r
-  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */\r
-  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;\r
-#elif defined (STM32F091xC) || defined (STM32F098xx)\r
-  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */\r
-  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;\r
-#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)\r
-  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */\r
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;\r
-#elif defined (STM32F051x8) || defined (STM32F058xx)\r
-  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */\r
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;\r
-#elif defined (STM32F042x6) || defined (STM32F048xx)\r
-  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */\r
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;\r
-#elif defined (STM32F070x6) || defined (STM32F070xB)\r
-  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */\r
-  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;\r
-  /* Set default USB clock to PLLCLK, since there is no HSI48 */\r
-  RCC->CFGR3 |= (uint32_t)0x00000080U;  \r
-#else\r
- #warning "No target selected"\r
-#endif\r
-\r
-  /* Reset HSI14 bit */\r
-  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;\r
-\r
-  /* Disable all interrupts */\r
-  RCC->CIR = 0x00000000U;\r
-\r
-}\r
-\r
-/**\r
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.\r
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can\r
-  *         be used by the user application to setup the SysTick timer or configure\r
-  *         other parameters.\r
-  *\r
-  * @note   Each time the core clock (HCLK) changes, this function must be called\r
-  *         to update SystemCoreClock variable value. Otherwise, any configuration\r
-  *         based on this variable will be incorrect.\r
-  *\r
-  * @note   - The system frequency computed by this function is not the real\r
-  *           frequency in the chip. It is calculated based on the predefined\r
-  *           constant and the selected clock source:\r
-  *\r
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\r
-  *\r
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\r
-  *\r
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)\r
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.\r
-  *\r
-  *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value\r
-  *             8 MHz) but the real value may vary depending on the variations\r
-  *             in voltage and temperature.\r
-  *\r
-  *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value\r
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real\r
-  *              frequency of the crystal used. Otherwise, this function may\r
-  *              have wrong result.\r
-  *\r
-  *         - The result of this function could be not correct when using fractional\r
-  *           value for HSE crystal.\r
-  *\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-void SystemCoreClockUpdate (void)\r
-{\r
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;\r
-\r
-  /* Get SYSCLK source -------------------------------------------------------*/\r
-  tmp = RCC->CFGR & RCC_CFGR_SWS;\r
-\r
-  switch (tmp)\r
-  {\r
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */\r
-      SystemCoreClock = HSI_VALUE;\r
-      break;\r
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */\r
-      SystemCoreClock = HSE_VALUE;\r
-      break;\r
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */\r
-      /* Get PLL clock source and multiplication factor ----------------------*/\r
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;\r
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
-      pllmull = ( pllmull >> 18) + 2;\r
-      predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;\r
-\r
-      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)\r
-      {\r
-        /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */\r
-        SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;\r
-      }\r
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)\r
-      else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)\r
-      {\r
-        /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */\r
-        SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;\r
-      }\r
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */\r
-      else\r
-      {\r
-#if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \\r
- || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \\r
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)\r
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */\r
-        SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;\r
-#else\r
-        /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */\r
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;\r
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || \r
-          STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||\r
-          STM32F091xC || STM32F098xx || STM32F030xC */\r
-      }\r
-      break;\r
-    default: /* HSI used as system clock */\r
-      SystemCoreClock = HSI_VALUE;\r
-      break;\r
-  }\r
-  /* Compute HCLK clock frequency ----------------*/\r
-  /* Get HCLK prescaler */\r
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
-  /* HCLK clock frequency */\r
-  SystemCoreClock >>= tmp;\r
-}\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
+/**
+  ******************************************************************************
+  * @file    system_stm32f0xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+  *
+  * 1. This file provides two functions and one global variable to be called from
+  *    user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f0xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. This file configures the system clock as follows:
+  *=============================================================================
+  *                         Supported STM32F0xx device
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | HSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 8000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 8000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx_system
+  * @{
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f0xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Defines
+  * @{
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+#if !defined (HSI48_VALUE)
+#define HSI48_VALUE    ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
+                                                 This value can be provided and adapted by the user application. */
+#endif /* HSI48_VALUE */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock there is no need to
+               call the 2 first functions listed above, since SystemCoreClock variable is 
+               updated automatically.
+  */
+uint32_t SystemCoreClock = 8000000;
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001U;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0xF8FFB80CU;
+#else
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+  RCC->CFGR &= (uint32_t)0x08FFB80CU;
+#endif /* STM32F051x8 or STM32F058x8 */
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFFU;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+  RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
+
+  /* Reset PREDIV[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
+#elif defined (STM32F071xB)
+  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
+  /* Set default USB clock to PLLCLK, since there is no HSI48 */
+  RCC->CFGR3 |= (uint32_t)0x00000080U;  
+#else
+ #warning "No target selected"
+#endif
+
+  /* Reset HSI14 bit */
+  RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000U;
+
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+      predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+
+      if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+      {
+        /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
+        SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
+      }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+      else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
+      {
+        /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
+        SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
+      }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+      else
+      {
+#if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) \
+ || defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) \
+ || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
+        /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
+        SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
+#else
+        /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 
+          STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
+          STM32F091xC || STM32F098xx || STM32F030xC */
+      }
+      break;
+    default: /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

diff --git a/startup_stm32f030x8.s b/startup_stm32f030x8.s
index 0e07033653efbc69f655ff3bae95bfdc8b568a18..e3fa93dfda81a0ff026dc2173eb30d34efc72306 100644 (file)
--- a/startup_stm32f030x8.s
+++ b/startup_stm32f030x8.s
@@ -1,286 +1,286 @@
-/**\r
-  ******************************************************************************\r
-  * @file      startup_stm32f030x8.s\r
-  * @author    MCD Application Team\r
-  * @brief     STM32F030x8 devices vector table for GCC toolchain.\r
-  *            This module performs:\r
-  *                - Set the initial SP\r
-  *                - Set the initial PC == Reset_Handler,\r
-  *                - Set the vector table entries with the exceptions ISR address\r
-  *                - Branches to main in the C library (which eventually\r
-  *                  calls main()).\r
-  *            After Reset the Cortex-M0 processor is in Thread mode,\r
-  *            priority is Privileged, and the Stack is set to Main.\r
-  ******************************************************************************\r
-  * \r
-  * Redistribution and use in source and binary forms, with or without modification,\r
-  * are permitted provided that the following conditions are met:\r
-  *   1. Redistributions of source code must retain the above copyright notice,\r
-  *      this list of conditions and the following disclaimer.\r
-  *   2. Redistributions in binary form must reproduce the above copyright notice,\r
-  *      this list of conditions and the following disclaimer in the documentation\r
-  *      and/or other materials provided with the distribution.\r
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors\r
-  *      may be used to endorse or promote products derived from this software\r
-  *      without specific prior written permission.\r
-  *\r
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
-  *\r
-  ******************************************************************************\r
-  */\r
-\r
-  .syntax unified\r
-  .cpu cortex-m0\r
-  .fpu softvfp\r
-  .thumb\r
-\r
-.global g_pfnVectors\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section.\r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */\r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-  .section .text.Reset_Handler\r
-  .weak Reset_Handler\r
-  .type Reset_Handler, %function\r
-Reset_Handler:\r
-  ldr   r0, =_estack\r
-  mov   sp, r0          /* set stack pointer */\r
-\r
-/* Copy the data segment initializers from flash to SRAM */\r
-  ldr r0, =_sdata\r
-  ldr r1, =_edata\r
-  ldr r2, =_sidata\r
-  movs r3, #0\r
-  b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
-  ldr r4, [r2, r3]\r
-  str r4, [r0, r3]\r
-  adds r3, r3, #4\r
-\r
-LoopCopyDataInit:\r
-  adds r4, r0, r3\r
-  cmp r4, r1\r
-  bcc CopyDataInit\r
-  \r
-/* Zero fill the bss segment. */\r
-  ldr r2, =_sbss\r
-  ldr r4, =_ebss\r
-  movs r3, #0\r
-  b LoopFillZerobss\r
-\r
-FillZerobss:\r
-  str  r3, [r2]\r
-  adds r2, r2, #4\r
-\r
-LoopFillZerobss:\r
-  cmp r2, r4\r
-  bcc FillZerobss\r
-\r
-/* Call the clock system intitialization function.*/\r
-  bl  SystemInit\r
-/* Call static constructors */\r
-  bl __libc_init_array\r
-/* Call the application's entry point.*/\r
-  bl main\r
-\r
-LoopForever:\r
-    b LoopForever\r
-\r
-\r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief  This is the code that gets called when the processor receives an\r
- *         unexpected interrupt.  This simply enters an infinite loop, preserving\r
- *         the system state for examination by a debugger.\r
- *\r
- * @param  None\r
- * @retval : None\r
-*/\r
-    .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
-  b Infinite_Loop\r
-  .size Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M0.  Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/\r
-   .section .isr_vector,"a",%progbits\r
-  .type g_pfnVectors, %object\r
-  .size g_pfnVectors, .-g_pfnVectors\r
-\r
-\r
-g_pfnVectors:\r
-  .word  _estack\r
-  .word  Reset_Handler\r
-  .word  NMI_Handler\r
-  .word  HardFault_Handler\r
-  .word  0\r
-  .word  0\r
-  .word  0\r
-  .word  0\r
-  .word  0\r
-  .word  0\r
-  .word  0\r
-  .word  SVC_Handler\r
-  .word  0\r
-  .word  0\r
-  .word  PendSV_Handler\r
-  .word  SysTick_Handler\r
-  .word  WWDG_IRQHandler                   /* Window WatchDog              */\r
-  .word  0                                 /* Reserved                     */\r
-  .word  RTC_IRQHandler                    /* RTC through the EXTI line    */\r
-  .word  FLASH_IRQHandler                  /* FLASH                        */\r
-  .word  RCC_IRQHandler                    /* RCC                          */\r
-  .word  EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */\r
-  .word  EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */\r
-  .word  EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */\r
-  .word  0                                 /* Reserved                     */\r
-  .word  DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */\r
-  .word  DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */\r
-  .word  DMA1_Channel4_5_IRQHandler        /* DMA1 Channel 4 and Channel 5 */\r
-  .word  ADC1_IRQHandler                   /* ADC1                         */\r
-  .word  TIM1_BRK_UP_TRG_COM_IRQHandler    /* TIM1 Break, Update, Trigger and Commutation */\r
-  .word  TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */\r
-  .word  0                                 /* Reserved                     */\r
-  .word  TIM3_IRQHandler                   /* TIM3                         */\r
-  .word  TIM6_IRQHandler                   /* TIM6                         */\r
-  .word  0                                 /* Reserved                     */\r
-  .word  TIM14_IRQHandler                  /* TIM14                        */\r
-  .word  TIM15_IRQHandler                  /* TIM15                        */\r
-  .word  TIM16_IRQHandler                  /* TIM16                        */\r
-  .word  TIM17_IRQHandler                  /* TIM17                        */\r
-  .word  I2C1_IRQHandler                   /* I2C1                         */\r
-  .word  I2C2_IRQHandler                   /* I2C2                         */\r
-  .word  SPI1_IRQHandler                   /* SPI1                         */\r
-  .word  SPI2_IRQHandler                   /* SPI2                         */\r
-  .word  USART1_IRQHandler                 /* USART1                       */\r
-  .word  USART2_IRQHandler                 /* USART2                       */\r
-  .word  0                                 /* Reserved                     */\r
-  .word  0                                 /* Reserved                     */\r
-  .word  0                                 /* Reserved                     */\r
-\r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler.\r
-* As they are weak aliases, any function with the same name will override\r
-* this definition.\r
-*\r
-*******************************************************************************/\r
-\r
-  .weak      NMI_Handler\r
-  .thumb_set NMI_Handler,Default_Handler\r
-\r
-  .weak      HardFault_Handler\r
-  .thumb_set HardFault_Handler,Default_Handler\r
-\r
-  .weak      SVC_Handler\r
-  .thumb_set SVC_Handler,Default_Handler\r
-\r
-  .weak      PendSV_Handler\r
-  .thumb_set PendSV_Handler,Default_Handler\r
-\r
-  .weak      SysTick_Handler\r
-  .thumb_set SysTick_Handler,Default_Handler\r
-\r
-  .weak      WWDG_IRQHandler\r
-  .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
-  .weak      RTC_IRQHandler\r
-  .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
-  .weak      FLASH_IRQHandler\r
-  .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
-  .weak      RCC_IRQHandler\r
-  .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
-  .weak      EXTI0_1_IRQHandler\r
-  .thumb_set EXTI0_1_IRQHandler,Default_Handler\r
-\r
-  .weak      EXTI2_3_IRQHandler\r
-  .thumb_set EXTI2_3_IRQHandler,Default_Handler\r
-\r
-  .weak      EXTI4_15_IRQHandler\r
-  .thumb_set EXTI4_15_IRQHandler,Default_Handler\r
-\r
-  .weak      DMA1_Channel1_IRQHandler\r
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
-  .weak      DMA1_Channel2_3_IRQHandler\r
-  .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler\r
-\r
-  .weak      DMA1_Channel4_5_IRQHandler\r
-  .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler\r
-\r
-  .weak      ADC1_IRQHandler\r
-  .thumb_set ADC1_IRQHandler,Default_Handler\r
-\r
-  .weak      TIM1_BRK_UP_TRG_COM_IRQHandler\r
-  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler\r
-\r
-  .weak      TIM1_CC_IRQHandler\r
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
-  .weak      TIM3_IRQHandler\r
-  .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
-  .weak      TIM6_IRQHandler\r
-  .thumb_set TIM6_IRQHandler,Default_Handler\r
-\r
-  .weak      TIM14_IRQHandler\r
-  .thumb_set TIM14_IRQHandler,Default_Handler\r
-\r
-  .weak      TIM15_IRQHandler\r
-  .thumb_set TIM15_IRQHandler,Default_Handler\r
-\r
-  .weak      TIM16_IRQHandler\r
-  .thumb_set TIM16_IRQHandler,Default_Handler\r
-\r
-  .weak      TIM17_IRQHandler\r
-  .thumb_set TIM17_IRQHandler,Default_Handler\r
-\r
-  .weak      I2C1_IRQHandler\r
-  .thumb_set I2C1_IRQHandler,Default_Handler\r
-\r
-  .weak      I2C2_IRQHandler\r
-  .thumb_set I2C2_IRQHandler,Default_Handler\r
-\r
-  .weak      SPI1_IRQHandler\r
-  .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
-  .weak      SPI2_IRQHandler\r
-  .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
-  .weak      USART1_IRQHandler\r
-  .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
-  .weak      USART2_IRQHandler\r
-  .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
-\r
+/**
+  ******************************************************************************
+  * @file      startup_stm32f030x8.s
+  * @author    MCD Application Team
+  * @brief     STM32F030x8 devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M0 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * 
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m0
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+  
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+
+LoopForever:
+    b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  0
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word  WWDG_IRQHandler                   /* Window WatchDog              */
+  .word  0                                 /* Reserved                     */
+  .word  RTC_IRQHandler                    /* RTC through the EXTI line    */
+  .word  FLASH_IRQHandler                  /* FLASH                        */
+  .word  RCC_IRQHandler                    /* RCC                          */
+  .word  EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
+  .word  EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
+  .word  EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
+  .word  0                                 /* Reserved                     */
+  .word  DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
+  .word  DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
+  .word  DMA1_Channel4_5_IRQHandler        /* DMA1 Channel 4 and Channel 5 */
+  .word  ADC1_IRQHandler                   /* ADC1                         */
+  .word  TIM1_BRK_UP_TRG_COM_IRQHandler    /* TIM1 Break, Update, Trigger and Commutation */
+  .word  TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word  0                                 /* Reserved                     */
+  .word  TIM3_IRQHandler                   /* TIM3                         */
+  .word  TIM6_IRQHandler                   /* TIM6                         */
+  .word  0                                 /* Reserved                     */
+  .word  TIM14_IRQHandler                  /* TIM14                        */
+  .word  TIM15_IRQHandler                  /* TIM15                        */
+  .word  TIM16_IRQHandler                  /* TIM16                        */
+  .word  TIM17_IRQHandler                  /* TIM17                        */
+  .word  I2C1_IRQHandler                   /* I2C1                         */
+  .word  I2C2_IRQHandler                   /* I2C2                         */
+  .word  SPI1_IRQHandler                   /* SPI1                         */
+  .word  SPI2_IRQHandler                   /* SPI2                         */
+  .word  USART1_IRQHandler                 /* USART1                       */
+  .word  USART2_IRQHandler                 /* USART2                       */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+  .word  0                                 /* Reserved                     */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak      RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak      FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak      RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak      EXTI0_1_IRQHandler
+  .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+  .weak      EXTI2_3_IRQHandler
+  .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+  .weak      EXTI4_15_IRQHandler
+  .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel2_3_IRQHandler
+  .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+  .weak      DMA1_Channel4_5_IRQHandler
+  .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
+
+  .weak      ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak      TIM1_BRK_UP_TRG_COM_IRQHandler
+  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+  .weak      TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak      TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak      TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      TIM15_IRQHandler
+  .thumb_set TIM15_IRQHandler,Default_Handler
+
+  .weak      TIM16_IRQHandler
+  .thumb_set TIM16_IRQHandler,Default_Handler
+
+  .weak      TIM17_IRQHandler
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      I2C1_IRQHandler
+  .thumb_set I2C1_IRQHandler,Default_Handler
+
+  .weak      I2C2_IRQHandler
+  .thumb_set I2C2_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak      SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak      USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak      USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+