pcilmr: Add margining process functions

pcilmr: Add margining process functions

* Implement the margining flow as described in the section "Example
  Software Flow for Lane Margining at Receiver"
  of the PCIe Base Spec Rev 5.0;
* Implement margining commands formation and response parsing according
  to the PCIe Base Spec Rev 5.0 table 4-26;
* Use Receiver margining parameters as described in the
  PCIe Base Spec Rev 5.0 table 8-11;
* Support lane reversal and simultaneous margining of several link lanes.

Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>