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(parent: 0a7350f) | patch
libpci: mmio-ports: Bypass CPU cache and add barriers for read/write
authorPali Rohár <pali@kernel.org>
Sat, 5 Nov 2022 16:32:38 +0000 (17:32 +0100)
committerPali Rohár <pali@kernel.org>
Fri, 18 Nov 2022 13:10:06 +0000 (14:10 +0100)
commit5d2ff7718d35f15636e231219d50d84fbd73ffb5
tree7b2cff6c2aef6a3e43d5c1a357f1c5b078175cf7tree | snapshot
parent0a7350fb9442dbfb8b0328ec9f7080947a28c2a1commit | diff
libpci: mmio-ports: Bypass CPU cache and add barriers for read/write

Between accessing address address and data I/O ports it is needed to issue
barriers. Use explicit readl() for barrier and O_DSYNC to bypass CPU cache.
lib/mmio-ports.c diff | blob | history
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