X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=lspci.c;h=aa6b37a8c1c42ceb47c14fcb72f536f090b94fec;hb=80e6c636fb1c5381f4ce95963ace48dc477c7599;hp=c61c1a0583d0729ec2d1e2dabe8f85d19e8e1ec6;hpb=044ed53845518829612aa6a46426dc0eced69fbd;p=pciutils.git diff --git a/lspci.c b/lspci.c index c61c1a0..aa6b37a 100644 --- a/lspci.c +++ b/lspci.c @@ -1,9 +1,7 @@ /* - * $Id: lspci.c,v 1.32 2000/01/13 22:50:13 mj Exp $ + * The PCI Utilities -- List All PCI Devices * - * Linux PCI Utilities -- List All PCI Devices - * - * Copyright (c) 1997--1999 Martin Mares + * Copyright (c) 1997--2004 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ @@ -34,8 +32,10 @@ Usage: lspci []\n\ -v\t\tBe verbose\n\ -n\t\tShow numeric ID's\n\ -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\ --x\t\tShow hex-dump of config space\n\ --s [[]:][][.[]]\tShow only devices in selected slots\n\ +-x\t\tShow hex-dump of the standard portion of config space\n\ +-xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\ +-xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\ +-s [[[[]:]]:][][.[]]\tShow only devices in selected slots\n\ -d []:[]\tShow only selected devices\n\ -t\t\tShow bus tree\n\ -m\t\tProduce machine-readable output\n\ @@ -48,30 +48,14 @@ GENERIC_HELP static struct pci_access *pacc; -/* Format strings used for IRQ numbers and memory addresses */ - -#ifdef ARCH_SPARC64 -#define IRQ_FORMAT "%08x" -#else -#define IRQ_FORMAT "%d" -#endif - -#ifdef HAVE_64BIT_ADDRESS -#ifdef HAVE_LONG_ADDRESS -#define ADDR_FORMAT "%016Lx" -#else -#define ADDR_FORMAT "%016lx" -#endif -#else -#define ADDR_FORMAT "%08lx" -#endif +/* + * If we aren't being compiled by GCC, use malloc() instead of alloca(). + * This increases our memory footprint, but only slightly since we don't + * use alloca() much. + */ -#ifdef ARCH_SPARC64 -#define IO_FORMAT "%016Lx" -#elif defined(HAVE_LONG_ADDRESS) -#define IO_FORMAT "%04Lx" -#else -#define IO_FORMAT "%04lx" +#ifndef __GNUC__ +#define alloca malloc #endif /* Our view of the PCI bus */ @@ -79,16 +63,34 @@ static struct pci_access *pacc; struct device { struct device *next; struct pci_dev *dev; - unsigned int config_cnt; - byte config[256]; + unsigned int config_cnt, config_bufsize; + byte *config; }; static struct device *first_dev; +static int +config_fetch(struct device *d, unsigned int pos, unsigned int len) +{ + unsigned int end = pos+len; + int result; + if (end <= d->config_cnt) + return 1; + if (end > d->config_bufsize) + { + while (end > d->config_bufsize) + d->config_bufsize *= 2; + d->config = xrealloc(d->config, d->config_bufsize); + } + result = pci_read_block(d->dev, pos, d->config + pos, len); + if (result && pos == d->config_cnt) + d->config_cnt = end; + return result; +} + static struct device * scan_device(struct pci_dev *p) { - int how_much = (show_hex > 2) ? 256 : 64; struct device *d; if (!pci_filter_match(&filter, p)) @@ -96,16 +98,17 @@ scan_device(struct pci_dev *p) d = xmalloc(sizeof(struct device)); bzero(d, sizeof(*d)); d->dev = p; - if (!pci_read_block(p, 0, d->config, how_much)) - die("Unable to read %d bytes of configuration space.", how_much); - if (how_much < 128 && (d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS) + d->config_cnt = d->config_bufsize = 64; + d->config = xmalloc(64); + if (!pci_read_block(p, 0, d->config, 64)) + die("Unable to read the configuration space header."); + if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS) { - /* For cardbus bridges, we need to fetch 64 bytes more to get the full standard header... */ - if (!pci_read_block(p, 0, d->config+64, 64)) + /* For cardbus bridges, we need to fetch 64 bytes more to get the + * full standard header... */ + if (!config_fetch(d, 64, 64)) die("Unable to read cardbus bridge extension data."); - how_much = 128; } - d->config_cnt = how_much; pci_setup_cache(p, d->config, d->config_cnt); pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES); return d; @@ -126,26 +129,6 @@ scan_devices(void) } } -static int -check_root(void) -{ - static int is_root = -1; - - if (is_root < 0) - is_root = !geteuid(); - return is_root; -} - -static int -config_fetch(struct device *d, unsigned int pos, unsigned int len) -{ - if (pos + len < d->config_cnt) - return 1; - if (pacc->method != PCI_ACCESS_DUMP && !check_root()) - return 0; - return pci_read_block(d->dev, pos, d->config + pos, len); -} - /* Config space accesses */ static inline byte @@ -177,6 +160,10 @@ compare_them(const void *A, const void *B) const struct pci_dev *a = (*(const struct device **)A)->dev; const struct pci_dev *b = (*(const struct device **)B)->dev; + if (a->domain < b->domain) + return -1; + if (a->domain > b->domain) + return 1; if (a->bus < b->bus) return -1; if (a->bus > b->bus) @@ -221,6 +208,16 @@ sort_them(void) #define FLAG(x,y) ((x & y) ? '+' : '-') +static void +show_slot_name(struct device *d) +{ + struct pci_dev *p = d->dev; + + if (p->domain) + printf("%04x:", p->domain); + printf("%02x:%02x.%d", p->bus, p->dev, p->func); +} + static void show_terse(struct device *d) { @@ -228,10 +225,8 @@ show_terse(struct device *d) struct pci_dev *p = d->dev; byte classbuf[128], devbuf[128]; - printf("%02x:%02x.%x %s: %s", - p->bus, - p->dev, - p->func, + show_slot_name(d); + printf(" %s: %s", pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0), @@ -271,7 +266,7 @@ show_size(pciaddr_t x) else if (x < 0x80000000) printf("%dM", (int)(x / 1048576)); else - printf(ADDR_FORMAT, x); + printf(PCIADDR_T_FMT, x); putchar(']'); } @@ -305,7 +300,7 @@ show_bases(struct device *d, int cnt) pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK; printf("I/O ports at "); if (a) - printf(IO_FORMAT, a); + printf(PCIADDR_PORT_FMT, a); else if (flg & PCI_BASE_ADDRESS_IO_MASK) printf(""); else @@ -335,7 +330,7 @@ show_bases(struct device *d, int cnt) if (buscentric_view) { if (a || z) - printf("%08x" ADDR_FORMAT, z, a); + printf("%08x" PCIADDR_T_FMT, z, a); else printf(""); done = 1; @@ -345,7 +340,7 @@ show_bases(struct device *d, int cnt) if (!done) { if (a) - printf(ADDR_FORMAT, a); + printf(PCIADDR_T_FMT, a); else printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "" : ""); } @@ -365,57 +360,559 @@ show_bases(struct device *d, int cnt) static void show_pm(struct device *d, int where, int cap) { - int t; + int t, b; + static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 }; printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK); if (verbose < 2) return; - printf("\t\tFlags: PMEClk%c AuxPwr%c DSI%c D1%c D2%c PME%c\n", + printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n", FLAG(cap, PCI_PM_CAP_PME_CLOCK), - FLAG(cap, PCI_PM_CAP_AUX_POWER), FLAG(cap, PCI_PM_CAP_DSI), FLAG(cap, PCI_PM_CAP_D1), FLAG(cap, PCI_PM_CAP_D2), - FLAG(cap, PCI_PM_CAP_PME)); - config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL); + pm_aux_current[(cap >> 6) & 7], + FLAG(cap, PCI_PM_CAP_PME_D0), + FLAG(cap, PCI_PM_CAP_PME_D1), + FLAG(cap, PCI_PM_CAP_PME_D2), + FLAG(cap, PCI_PM_CAP_PME_D3_HOT), + FLAG(cap, PCI_PM_CAP_PME_D3_COLD)); + if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL)) + return; t = get_conf_word(d, where + PCI_PM_CTRL); - printf("\t\tStatus: D%d PME-Enable%c DSel=%x DScale=%x PME%c\n", + printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n", t & PCI_PM_CTRL_STATE_MASK, FLAG(t, PCI_PM_CTRL_PME_ENABLE), (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9, (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13, FLAG(t, PCI_PM_CTRL_PME_STATUS)); + b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS); + if (b) + printf("\t\tBridge: PM%c B3%c\n", + FLAG(t, PCI_PM_BPCC_ENABLE), + FLAG(~t, PCI_PM_PPB_B2_B3)); +} + +static void +format_agp_rate(int rate, char *buf, int agp3) +{ + char *c = buf; + int i; + + for(i=0; i<=2; i++) + if (rate & (1 << i)) + { + if (c != buf) + *c++ = ','; + c += sprintf(c, "x%d", 1 << (i + 2*agp3)); + } + if (c != buf) + *c = 0; + else + strcpy(buf, ""); } static void show_agp(struct device *d, int where, int cap) { u32 t; + char rate[16]; + int ver, rev; + int agp3 = 0; - t = cap & 0xff; - printf("AGP version %x.%x\n", cap/16, cap%16); + ver = (cap >> 4) & 0x0f; + rev = cap & 0x0f; + printf("AGP version %x.%x\n", ver, rev); if (verbose < 2) return; - config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS); + if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS)) + return; t = get_conf_long(d, where + PCI_AGP_STATUS); - printf("\t\tStatus: RQ=%d SBA%c 64bit%c FW%c Rate=%s%s%s\n", - (t & PCI_AGP_STATUS_RQ_MASK) >> 24U, + if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3)) + agp3 = 1; + format_agp_rate(t & 7, rate, agp3); + printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n", + ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1, + FLAG(t, PCI_AGP_STATUS_ISOCH), + ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13), + ((t & PCI_AGP_STATUS_CAL_MASK) >> 10), FLAG(t, PCI_AGP_STATUS_SBA), + FLAG(t, PCI_AGP_STATUS_ITA_COH), + FLAG(t, PCI_AGP_STATUS_GART64), + FLAG(t, PCI_AGP_STATUS_HTRANS), FLAG(t, PCI_AGP_STATUS_64BIT), FLAG(t, PCI_AGP_STATUS_FW), - (t & PCI_AGP_STATUS_RATE4) ? "4" : "", - (t & PCI_AGP_STATUS_RATE2) ? "2" : "", - (t & PCI_AGP_STATUS_RATE1) ? "1" : ""); + FLAG(t, PCI_AGP_STATUS_AGP3), + rate); t = get_conf_long(d, where + PCI_AGP_COMMAND); - printf("\t\tCommand: RQ=%d SBA%c AGP%c 64bit%c FW%c Rate=%s%s%s\n", - (t & PCI_AGP_COMMAND_RQ_MASK) >> 24U, + format_agp_rate(t & 7, rate, agp3); + printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n", + ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1, + ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13), + ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10), FLAG(t, PCI_AGP_COMMAND_SBA), FLAG(t, PCI_AGP_COMMAND_AGP), + FLAG(t, PCI_AGP_COMMAND_GART64), FLAG(t, PCI_AGP_COMMAND_64BIT), FLAG(t, PCI_AGP_COMMAND_FW), - (t & PCI_AGP_COMMAND_RATE4) ? "4" : "", - (t & PCI_AGP_COMMAND_RATE2) ? "2" : "", - (t & PCI_AGP_COMMAND_RATE1) ? "1" : ""); + rate); +} + +static void +show_pcix_nobridge(struct device *d, int where) +{ + u16 command; + u32 status; + + printf("PCI-X non-bridge device.\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_PCIX_STATUS, 4)) + return; + + command = get_conf_word(d, where + PCI_PCIX_COMMAND); + status = get_conf_long(d, where + PCI_PCIX_STATUS); + printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n", + FLAG(command, PCI_PCIX_COMMAND_DPERE), + FLAG(command, PCI_PCIX_COMMAND_ERO), + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U), + ((command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U)); + printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, DC=%s, DMMRBC=%u, DMOST=%u, DMCRS=%u, RSCEM%c\n", + ((status >> 8) & 0xffU), // bus + ((status >> 3) & 0x1fU), // dev + (status & PCI_PCIX_STATUS_FUNCTION), // function + FLAG(status, PCI_PCIX_STATUS_64BIT), + FLAG(status, PCI_PCIX_STATUS_133MHZ), + FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED), + FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC), + ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"), + ((status >> 21) & 3U), + ((status >> 23) & 7U), + ((status >> 26) & 7U), + FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS)); +} + +static void +show_pcix_bridge(struct device *d, int where) +{ + + u16 secstatus; + u32 status, upstcr, downstcr; + + printf("PCI-X bridge device.\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12)) + return; + + secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS); + printf("\t\tSecondary Status: 64bit%c, 133MHz%c, SCD%c, USC%c, SCO%c, SRD%c Freq=%d\n", + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT), + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ), + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED), + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC), + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN), + FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED), + ((secstatus >> 6) & 7)); + status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS); + printf("\t\tStatus: Bus=%u Dev=%u Func=%u 64bit%c 133MHz%c SCD%c USC%c, SCO%c, SRD%c\n", + ((status >> 8) & 0xff), // bus + ((status >> 3) & 0x1f), // dev + (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), // function + FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT), + FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ), + FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED), + FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC), + FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN), + FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED)); + upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL); + printf("\t\t: Upstream: Capacity=%u, Commitment Limit=%u\n", + (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY), + (upstcr >> 16) & 0xffff); + downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL); + printf("\t\t: Downstream: Capacity=%u, Commitment Limit=%u\n", + (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY), + (downstcr >> 16) & 0xffff); +} + +static void +show_pcix(struct device *d, int where) +{ + switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f) + { + case PCI_HEADER_TYPE_NORMAL: + show_pcix_nobridge(d, where); + break; + case PCI_HEADER_TYPE_BRIDGE: + show_pcix_bridge(d, where); + break; + } +} + +static inline char * +ht_link_width(unsigned width) +{ + static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" }; + return widths[width]; +} + +static inline char * +ht_link_freq(unsigned freq) +{ + static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz", + "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" }; + return freqs[freq]; +} + +static void +show_ht_pri(struct device *d, int where, int cmd) +{ + u16 lctr0, lcnf0, lctr1, lcnf1, eh; + u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn; + char *fmt; + + printf("HyperTransport: Slave or Primary Interface\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0)) + return; + rid = get_conf_byte(d, where + PCI_HT_PRI_RID); + if (rid < 0x23 && rid > 0x11) + printf("\t!!! Possibly incomplete decoding\n"); + + if (rid >= 0x23) + fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n"; + else + fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n"; + printf(fmt, + (cmd & PCI_HT_PRI_CMD_BUID), + (cmd & PCI_HT_PRI_CMD_UC) >> 5, + FLAG(cmd, PCI_HT_PRI_CMD_MH), + FLAG(cmd, PCI_HT_PRI_CMD_DD), + FLAG(cmd, PCI_HT_PRI_CMD_DUL)); + lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0); + if (rid >= 0x23) + fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c > 8, + FLAG(lctr0, PCI_HT_LCTR_ISOCEN), + FLAG(lctr0, PCI_HT_LCTR_LSEN), + FLAG(lctr0, PCI_HT_LCTR_EXTCTL), + FLAG(lctr0, PCI_HT_LCTR_64B)); + lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0); + if (rid >= 0x23) + fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n"; + else + fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n"; + printf(fmt, + ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI), + ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4), + ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8), + ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12), + FLAG(lcnf0, PCI_HT_LCNF_DFI), + FLAG(lcnf0, PCI_HT_LCNF_DFO), + FLAG(lcnf0, PCI_HT_LCNF_DFIE), + FLAG(lcnf0, PCI_HT_LCNF_DFOE)); + lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1); + if (rid >= 0x23) + fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c > 8, + FLAG(lctr1, PCI_HT_LCTR_ISOCEN), + FLAG(lctr1, PCI_HT_LCTR_LSEN), + FLAG(lctr1, PCI_HT_LCTR_EXTCTL), + FLAG(lctr1, PCI_HT_LCTR_64B)); + lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1); + if (rid >= 0x23) + fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n"; + else + fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n"; + printf(fmt, + ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI), + ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4), + ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8), + ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12), + FLAG(lcnf1, PCI_HT_LCNF_DFI), + FLAG(lcnf1, PCI_HT_LCNF_DFO), + FLAG(lcnf1, PCI_HT_LCNF_DFIE), + FLAG(lcnf1, PCI_HT_LCNF_DFOE)); + printf("\t\tRevision ID: %u.%02u\n", + (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN)); + if (rid < 0x23) + return; + lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0); + printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ)); + printf("\t\tLink Error 0: 0x11) + printf("\t!!! Possibly incomplete decoding\n"); + + if (rid >= 0x23) + fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c > 2, + FLAG(cmd, PCI_HT_SEC_CMD_CS), + FLAG(cmd, PCI_HT_SEC_CMD_HH), + FLAG(cmd, PCI_HT_SEC_CMD_AS), + FLAG(cmd, PCI_HT_SEC_CMD_HIECE), + FLAG(cmd, PCI_HT_SEC_CMD_DUL)); + lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR); + if (rid >= 0x23) + fmt = "\t\tLink Control: CFlE%c CST%c CFE%c > 8, + FLAG(lctr, PCI_HT_LCTR_ISOCEN), + FLAG(lctr, PCI_HT_LCTR_LSEN), + FLAG(lctr, PCI_HT_LCTR_EXTCTL), + FLAG(lctr, PCI_HT_LCTR_64B)); + lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF); + if (rid >= 0x23) + fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n"; + else + fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n"; + printf(fmt, + ht_link_width(lcnf & PCI_HT_LCNF_MLWI), + ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4), + ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8), + ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12), + FLAG(lcnf, PCI_HT_LCNF_DFI), + FLAG(lcnf, PCI_HT_LCNF_DFO), + FLAG(lcnf, PCI_HT_LCNF_DFIE), + FLAG(lcnf, PCI_HT_LCNF_DFOE)); + printf("\t\tRevision ID: %u.%02u\n", + (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN)); + if (rid < 0x23) + return; + lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER); + printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ)); + printf("\t\tLink Error: > 5, (cmd & PCI_HT_RID_MIN)); + break; + case PCI_HT_CMD_TYP_UIDC: + printf("HyperTransport: UnitID Clumping\n"); + break; + case PCI_HT_CMD_TYP_ECSA: + printf("HyperTransport: Extended Configuration Space Access\n"); + break; + case PCI_HT_CMD_TYP_AM: + printf("HyperTransport: Address Mapping\n"); + break; + case PCI_HT_CMD_TYP_MSIM: + printf("HyperTransport: MSI Mapping\n"); + break; + case PCI_HT_CMD_TYP_DR: + printf("HyperTransport: DirectRoute\n"); + break; + case PCI_HT_CMD_TYP_VCS: + printf("HyperTransport: VCSet\n"); + break; + case PCI_HT_CMD_TYP_RM: + printf("HyperTransport: Retry Mode\n"); + break; + case PCI_HT_CMD_TYP_X86: + printf("HyperTransport: X86 (reserved)\n"); + break; + default: + printf("HyperTransport: #%02x\n", type >> 11); + } } static void @@ -429,7 +926,7 @@ show_rom(struct device *d) return; printf("\tExpansion ROM at "); if (rom & PCI_ROM_ADDRESS_MASK) - printf(ADDR_FORMAT, rom & PCI_ROM_ADDRESS_MASK); + printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK); else printf(""); if (!(rom & PCI_ROM_ADDRESS_ENABLE)) @@ -453,7 +950,8 @@ show_msi(struct device *d, int where, int cap) if (verbose < 2) return; is64 = cap & PCI_MSI_FLAGS_64BIT; - config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO); + if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO)) + return; printf("\t\tAddress: "); if (is64) { @@ -467,6 +965,251 @@ show_msi(struct device *d, int where, int cap) printf("%08x Data: %04x\n", t, w); } +static void show_vendor(void) +{ + printf("Vendor Specific Information\n"); +} + +static void show_debug(void) +{ + printf("Debug port\n"); +} + +static float power_limit(int value, int scale) +{ + static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 }; + return value * scales[scale]; +} + +static const char *latency_l0s(int value) +{ + static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" }; + return latencies[value]; +} + +static const char *latency_l1(int value) +{ + static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" }; + return latencies[value]; +} + +static void show_express_dev(struct device *d, int where, int type) +{ + u32 t; + u16 w; + + t = get_conf_long(d, where + PCI_EXP_DEVCAP); + printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n", + 128 << (t & PCI_EXP_DEVCAP_PAYLOAD), + (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1, + FLAG(t, PCI_EXP_DEVCAP_EXT_TAG)); + printf("\t\tDevice: Latency L0s %s, L1 %s\n", + latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6), + latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9)); + if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || + (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE)) + printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n", + FLAG(t, PCI_EXP_DEVCAP_ATN_BUT), + FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND)); + if (type == PCI_EXP_TYPE_UPSTREAM) + printf("\t\tDevice: SlotPowerLimit %f\n", + power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, + (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26)); + + w = get_conf_word(d, where + PCI_EXP_DEVCTL); + printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n", + FLAG(w, PCI_EXP_DEVCTL_CERE), + FLAG(w, PCI_EXP_DEVCTL_NFERE), + FLAG(w, PCI_EXP_DEVCTL_FERE), + FLAG(w, PCI_EXP_DEVCTL_URRE)); + printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n", + FLAG(w, PCI_EXP_DEVCTL_RELAXED), + FLAG(w, PCI_EXP_DEVCTL_EXT_TAG), + FLAG(w, PCI_EXP_DEVCTL_PHANTOM), + FLAG(w, PCI_EXP_DEVCTL_AUX_PME), + FLAG(w, PCI_EXP_DEVCTL_NOSNOOP)); + printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n", + 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5), + 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12)); +} + +static char *link_speed(int speed) +{ + switch (speed) + { + case 1: + return "2.5Gb/s"; + default: + return "unknown"; + } +} + +static char *aspm_support(int code) +{ + switch (code) + { + case 1: + return "L0s"; + case 3: + return "L0s L1"; + default: + return "unknown"; + } +} + +static const char *aspm_enabled(int code) +{ + static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" }; + return desc[code]; +} + +static void show_express_link(struct device *d, int where, int type) +{ + u32 t; + u16 w; + + t = get_conf_long(d, where + PCI_EXP_LNKCAP); + printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n", + link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4, + aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10), + t >> 24); + printf("\t\tLink: Latency L0s %s, L1 %s\n", + latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12), + latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15)); + w = get_conf_word(d, where + PCI_EXP_LNKCTL); + printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM)); + if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) || + (type == PCI_EXP_TYPE_LEG_END)) + printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64); + if (w & PCI_EXP_LNKCTL_DISABLE) + printf(" Disabled"); + printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK), + FLAG(w, PCI_EXP_LNKCTL_XSYNCH)); + w = get_conf_word(d, where + PCI_EXP_LNKSTA); + printf("\t\tLink: Speed %s, Width x%d\n", + link_speed(t & PCI_EXP_LNKSTA_SPEED), (t & PCI_EXP_LNKSTA_WIDTH) >> 4); +} + +static const char *indicator(int code) +{ + static const char *names[] = { "Unknown", "On", "Blink", "Off" }; + return names[code]; +} + +static void show_express_slot(struct device *d, int where) +{ + u32 t; + u16 w; + + t = get_conf_long(d, where + PCI_EXP_SLTCAP); + printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n", + FLAG(t, PCI_EXP_SLTCAP_ATNB), + FLAG(t, PCI_EXP_SLTCAP_PWRC), + FLAG(t, PCI_EXP_SLTCAP_MRL), + FLAG(t, PCI_EXP_SLTCAP_ATNI), + FLAG(t, PCI_EXP_SLTCAP_PWRI), + FLAG(t, PCI_EXP_SLTCAP_HPC), + FLAG(t, PCI_EXP_SLTCAP_HPS)); + printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19, + power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, + (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15)); + w = get_conf_word(d, where + PCI_EXP_SLTCTL); + printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n", + FLAG(w, PCI_EXP_SLTCTL_ATNB), + FLAG(w, PCI_EXP_SLTCTL_PWRF), + FLAG(w, PCI_EXP_SLTCTL_MRLS), + FLAG(w, PCI_EXP_SLTCTL_PRSD), + FLAG(w, PCI_EXP_SLTCTL_CMDC), + FLAG(w, PCI_EXP_SLTCTL_HPIE)); + printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n", + indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6), + indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8), + FLAG(w, w & PCI_EXP_SLTCTL_PWRC)); +} + +static void show_express_root(struct device *d, int where) +{ + u16 w = get_conf_word(d, where + PCI_EXP_RTCTL); + printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n", + FLAG(w, PCI_EXP_RTCTL_SECEE), + FLAG(w, PCI_EXP_RTCTL_SENFEE), + FLAG(w, PCI_EXP_RTCTL_SEFEE), + FLAG(w, PCI_EXP_RTCTL_PMEIE)); +} + +static void +show_express(struct device *d, int where, int cap) +{ + int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4; + int size; + int slot = 0; + + printf("Express "); + switch (type) + { + case PCI_EXP_TYPE_ENDPOINT: + printf("Endpoint"); + break; + case PCI_EXP_TYPE_LEG_END: + printf("Legacy Endpoint"); + break; + case PCI_EXP_TYPE_ROOT_PORT: + slot = cap & PCI_EXP_FLAGS_SLOT; + printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT)); + break; + case PCI_EXP_TYPE_UPSTREAM: + printf("Upstream Port"); + break; + case PCI_EXP_TYPE_DOWNSTREAM: + slot = cap & PCI_EXP_FLAGS_SLOT; + printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT)); + break; + case PCI_EXP_TYPE_PCI_BRIDGE: + printf("PCI/PCI-X Bridge"); + break; + default: + printf("Unknown type"); + } + printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9); + if (verbose < 2) + return; + + size = 16; + if (slot) + size = 24; + if (type == PCI_EXP_TYPE_ROOT_PORT) + size = 32; + if (!config_fetch(d, where + PCI_EXP_DEVCAP, size)) + return; + + show_express_dev(d, where, type); + show_express_link(d, where, type); + if (slot) + show_express_slot(d, where); + if (type == PCI_EXP_TYPE_ROOT_PORT) + show_express_root(d, where); +} + +static void +show_msix(struct device *d, int where, int cap) +{ + u32 off; + + printf("MSI-X: Enable%c Mask%c TabSize=%d\n", + FLAG(cap, PCI_MSIX_ENABLE), + FLAG(cap, PCI_MSIX_MASK), + (cap & PCI_MSIX_TABSIZE) + 1); + if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8)) + return; + + off = get_conf_long(d, where + PCI_MSIX_TABLE); + printf("\t\tVector table: BAR=%d offset=%08x\n", + off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR); + off = get_conf_long(d, where + PCI_MSIX_PBA); + printf("\t\tPBA: BAR=%d offset=%08x\n", + off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR); +} + static void show_slotid(int cap) { @@ -479,6 +1222,75 @@ show_slotid(int cap) chs); } +static void +show_aer(struct device *d, int where) +{ + printf("Advanced Error Reporting\n"); +} + +static void +show_vc(struct device *d, int where) +{ + printf("Virtual Channel\n"); +} + +static void +show_dsn(struct device *d, int where) +{ + u32 t1, t2; + if (!config_fetch(d, where + 4, 8)) + return; + t1 = get_conf_long(d, where + 4); + t2 = get_conf_long(d, where + 8); + printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", + t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24, + t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24); +} + +static void +show_pb(struct device *d, int where) +{ + printf("Power Budgeting\n"); +} + +static void +show_ext_caps(struct device *d) +{ + int where = 0x100; + do + { + u32 header; + int id; + + if (!config_fetch(d, where, 4)) + break; + header = get_conf_long(d, where); + if (!header) + break; + id = header & 0xffff; + printf("\tCapabilities: [%03x] ", where); + switch (id) + { + case PCI_EXT_CAP_ID_AER: + show_aer(d, where); + break; + case PCI_EXT_CAP_ID_VC: + show_vc(d, where); + break; + case PCI_EXT_CAP_ID_DSN: + show_dsn(d, where); + break; + case PCI_EXT_CAP_ID_PB: + show_pb(d, where); + break; + default: + printf("Unknown (%d)\n", id); + break; + } + where = header >> 20; + } while (where); +} + static void show_caps(struct device *d) { @@ -520,12 +1332,31 @@ show_caps(struct device *d) case PCI_CAP_ID_MSI: show_msi(d, where, cap); break; + case PCI_CAP_ID_PCIX: + show_pcix(d, where); + break; + case PCI_CAP_ID_HT: + show_ht(d, where, cap); + break; + case PCI_CAP_ID_VNDR: + show_vendor(); + break; + case PCI_CAP_ID_DBG: + show_debug(); + break; + case PCI_CAP_ID_EXP: + show_express(d, where, cap); + break; + case PCI_CAP_ID_MSIX: + show_msix(d, where, cap); + break; default: printf("#%02x [%04x]\n", id, cap); } where = next; } } + show_ext_caps(d); } static void @@ -548,6 +1379,7 @@ show_htype1(struct device *d) u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE); u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT); u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK; + word sec_stat = get_conf_word(d, PCI_SEC_STATUS); word brc = get_conf_word(d, PCI_BRIDGE_CONTROL); int verb = verbose > 2; @@ -605,8 +1437,19 @@ show_htype1(struct device *d) } } - if (get_conf_word(d, PCI_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR) - printf("\tSecondary status: SERR\n"); + if (verbose > 1) + printf("\tSecondary status: 66Mhz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c base || verb) - printf("Memory window %d: %08x-%08x%s%s\n", i, base, limit, + printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit, (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]", (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : ""); } @@ -704,25 +1547,21 @@ show_verbose(struct device *d) { case PCI_HEADER_TYPE_NORMAL: if (class == PCI_CLASS_BRIDGE_PCI) - { - badhdr: - printf("\t!!! Header type %02x doesn't match class code %04x\n", htype, class); - return; - } + printf("\t!!! Invalid class %04x for header type %02x\n", class, htype); max_lat = get_conf_byte(d, PCI_MAX_LAT); min_gnt = get_conf_byte(d, PCI_MIN_GNT); subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID); subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID); break; case PCI_HEADER_TYPE_BRIDGE: - if (class != PCI_CLASS_BRIDGE_PCI) - goto badhdr; + if ((class >> 8) != PCI_BASE_CLASS_BRIDGE) + printf("\t!!! Invalid class %04x for header type %02x\n", class, htype); irq = int_pin = min_gnt = max_lat = 0; subsys_v = subsys_d = 0; break; case PCI_HEADER_TYPE_CARDBUS: if ((class >> 8) != PCI_BASE_CLASS_BRIDGE) - goto badhdr; + printf("\t!!! Invalid class %04x for header type %02x\n", class, htype); min_gnt = max_lat = 0; subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID); subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID); @@ -767,18 +1606,24 @@ show_verbose(struct device *d) FLAG(status, PCI_STATUS_DETECTED_PARITY)); if (cmd & PCI_COMMAND_MASTER) { - printf("\tLatency: "); - if (min_gnt) - printf("%d min, ", min_gnt); - if (max_lat) - printf("%d max, ", max_lat); - printf("%d set", latency); + printf("\tLatency: %d", latency); + if (min_gnt || max_lat) + { + printf(" ("); + if (min_gnt) + printf("%dns min", min_gnt*250); + if (min_gnt && max_lat) + printf(", "); + if (max_lat) + printf("%dns max", max_lat*250); + putchar(')'); + } if (cache_line) - printf(", cache line size %02x", cache_line); + printf(", Cache Line Size %02x", cache_line); putchar('\n'); } if (int_pin || irq) - printf("\tInterrupt: pin %c routed to IRQ " IRQ_FORMAT "\n", + printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n", (int_pin ? 'A' + int_pin - 1 : '?'), irq); } else @@ -803,7 +1648,7 @@ show_verbose(struct device *d) if (cmd & PCI_COMMAND_MASTER) printf(", latency %d", latency); if (irq) - printf(", IRQ " IRQ_FORMAT, irq); + printf(", IRQ " PCIIRQ_FMT, irq); putchar('\n'); } @@ -832,9 +1677,17 @@ show_verbose(struct device *d) static void show_hex_dump(struct device *d) { - unsigned int i; + unsigned int i, cnt; + + cnt = d->config_cnt; + if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt)) + { + cnt = 256; + if (show_hex >= 4 && config_fetch(d, 256, 4096-256)) + cnt = 4096; + } - for(i=0; iconfig_cnt; i++) + for(i=0; ibus, p->dev, p->func); + printf("Device:\t"); + show_slot_name(d); + putchar('\n'); printf("Class:\t%s\n", pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0)); printf("Vendor:\t%s\n", @@ -887,8 +1742,8 @@ show_machine(struct device *d) } else { - printf("%02x:%02x.%x ", p->bus, p->dev, p->func); - printf("\"%s\" \"%s\" \"%s\"", + show_slot_name(d); + printf(" \"%s\" \"%s\" \"%s\"", pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, get_conf_word(d, PCI_CLASS_DEVICE), 0, 0, 0), pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, @@ -939,35 +1794,38 @@ struct bridge { struct bridge *chain; /* Single-linked list of bridges */ struct bridge *next, *child; /* Tree of bridges */ struct bus *first_bus; /* List of busses connected to this bridge */ + unsigned int domain; unsigned int primary, secondary, subordinate; /* Bus numbers */ struct device *br_dev; }; struct bus { + unsigned int domain; unsigned int number; struct bus *sibling; struct device *first_dev, **last_dev; }; -static struct bridge host_bridge = { NULL, NULL, NULL, NULL, ~0, 0, ~0, NULL }; +static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL }; static struct bus * -find_bus(struct bridge *b, unsigned int n) +find_bus(struct bridge *b, unsigned int domain, unsigned int n) { struct bus *bus; for(bus=b->first_bus; bus; bus=bus->sibling) - if (bus->number == n) + if (bus->domain == domain && bus->number == n) break; return bus; } static struct bus * -new_bus(struct bridge *b, unsigned int n) +new_bus(struct bridge *b, unsigned int domain, unsigned int n) { struct bus *bus = xmalloc(sizeof(struct bus)); bus = xmalloc(sizeof(struct bus)); + bus->domain = domain; bus->number = n; bus->sibling = b->first_bus; bus->first_dev = NULL; @@ -982,16 +1840,19 @@ insert_dev(struct device *d, struct bridge *b) struct pci_dev *p = d->dev; struct bus *bus; - if (! (bus = find_bus(b, p->bus))) + if (! (bus = find_bus(b, p->domain, p->bus))) { struct bridge *c; for(c=b->child; c; c=c->next) - if (c->secondary <= p->bus && p->bus <= c->subordinate) - return insert_dev(d, c); - bus = new_bus(b, p->bus); + if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate) + { + insert_dev(d, c); + return; + } + bus = new_bus(b, p->domain, p->bus); } /* Simple insertion at the end _does_ guarantee the correct order as the - * original device list was sorted by (bus, devfn) lexicographically + * original device list was sorted by (domain, bus, devfn) lexicographically * and all devices on the new list have the same bus number. */ *bus->last_dev = d; @@ -1016,6 +1877,7 @@ grow_tree(void) (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS)) { b = xmalloc(sizeof(struct bridge)); + b->domain = d->dev->domain; if (ht == PCI_HEADER_TYPE_BRIDGE) { b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS); @@ -1044,7 +1906,8 @@ grow_tree(void) struct bridge *c, *best; best = NULL; for(c=&host_bridge; c; c=c->chain) - if (c != b && b->primary >= c->secondary && b->primary <= c->subordinate && + if (c != b && (c == &host_bridge || b->domain == c->domain) && + b->primary >= c->secondary && b->primary <= c->subordinate && (!best || best->subordinate - best->primary > c->subordinate - c->primary)) best = c; if (best) @@ -1057,8 +1920,8 @@ grow_tree(void) /* Insert secondary bus for each bridge */ for(b=&host_bridge; b; b=b->chain) - if (!find_bus(b, b->secondary)) - new_bus(b, b->secondary); + if (!find_bus(b, b->domain, b->secondary)) + new_bus(b, b->domain, b->secondary); /* Create bus structs and link devices */ @@ -1097,9 +1960,9 @@ show_tree_dev(struct device *d, byte *line, byte *p) if (b->br_dev == d) { if (b->secondary == b->subordinate) - p += sprintf(p, "-[%02x]-", b->secondary); + p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary); else - p += sprintf(p, "-[%02x-%02x]-", b->secondary, b->subordinate); + p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate); show_tree_bridge(b, line, p); return; } @@ -1145,7 +2008,7 @@ show_tree_bridge(struct bridge *b, byte *line, byte *p) if (!b->first_bus->sibling) { if (b == &host_bridge) - p += sprintf(p, "[%02x]-", b->first_bus->number); + p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number); show_tree_bus(b->first_bus, line, p); } else @@ -1155,11 +2018,11 @@ show_tree_bridge(struct bridge *b, byte *line, byte *p) while (u->sibling) { - k = p + sprintf(p, "+-[%02x]-", u->number); + k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number); show_tree_bus(u, line, k); u = u->sibling; } - k = p + sprintf(p, "\\-[%02x]-", u->number); + k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number); show_tree_bus(u, line, k); } } @@ -1229,7 +2092,8 @@ do_map_bus(int bus) for(func = 0; func < func_limit; func++) if (filter.func < 0 || filter.func == func) { - struct pci_dev *p = pci_get_dev(pacc, bus, dev, func); + /* XXX: Bus mapping supports only domain 0 */ + struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func); u16 vendor = pci_read_word(p, PCI_VENDOR_ID); if (vendor && vendor != 0xffff) { @@ -1328,8 +2192,6 @@ map_the_bus(void) if (pacc->method == PCI_ACCESS_PROC_BUS_PCI || pacc->method == PCI_ACCESS_DUMP) printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n"); - else if (!check_root()) - die("Only root can map the bus."); bus_info = xmalloc(sizeof(struct bus_info) * 256); bzero(bus_info, sizeof(struct bus_info) * 256); if (filter.bus >= 0) @@ -1376,7 +2238,7 @@ main(int argc, char **argv) break; case 's': if (msg = pci_filter_parse_slot(&filter, optarg)) - die("-f: %s", msg); + die("-s: %s", msg); break; case 'd': if (msg = pci_filter_parse_id(&filter, optarg))