X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=ls-ecaps.c;h=ef22b13bc7c640d48ee639fd9d636da298fb3def;hb=44c6c7fcfe0f9219447ac78e3f386e3223328149;hp=800a0322e1b77076bd2b8a28b12e56bf85762e97;hpb=aca48104492b5bfc16eba29dce8f9134ac7641c9;p=pciutils.git diff --git a/ls-ecaps.c b/ls-ecaps.c index 800a032..ef22b13 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -1,7 +1,7 @@ /* * The PCI Utilities -- Show Extended Capabilities * - * Copyright (c) 1997--2010 Martin Mares + * Copyright (c) 1997--2020 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ @@ -76,6 +76,37 @@ cap_ltr(struct device *d, int where) ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale); } +static void +cap_sec(struct device *d, int where) +{ + u32 ctrl3, lane_err_stat; + u8 lane; + printf("Secondary PCI Express\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12)) + return; + + ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3); + printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n", + FLAG(ctrl3, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN), + FLAG(ctrl3, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU)); + + lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR); + printf("\t\tLaneErrStat: "); + if (lane_err_stat) + { + printf("LaneErr at lane:"); + for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1) + if (BITS(lane_err_stat, 0, 1)) + printf(" %u", lane); + } + else + printf("0"); + printf("\n"); +} + static void cap_dsn(struct device *d, int where) { @@ -396,6 +427,62 @@ cap_sriov(struct device *d, int where) PCI_IOV_MSA_BIR(l)); } +static void +cap_multicast(struct device *d, int where, int type) +{ + u16 w; + u32 l; + u64 bar, rcv, block; + + printf("Multicast\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30)) + return; + + w = get_conf_word(d, where + PCI_MCAST_CAP); + printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1); + if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP) + printf(", WindowSz %d (%d bytes)", + PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w)); + if (type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM) + printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC)); + w = get_conf_word(d, where + PCI_MCAST_CTRL); + printf("\t\tMcastCtl: NumGroups %d, Enable%c\n", + PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE)); + bar = get_conf_long(d, where + PCI_MCAST_BAR); + l = get_conf_long(d, where + PCI_MCAST_BAR + 4); + bar |= (u64) l << 32; + printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n", + PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK); + rcv = get_conf_long(d, where + PCI_MCAST_RCV); + l = get_conf_long(d, where + PCI_MCAST_RCV + 4); + rcv |= (u64) l << 32; + printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X "\n", rcv); + block = get_conf_long(d, where + PCI_MCAST_BLOCK); + l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4); + block |= (u64) l << 32; + printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X "\n", block); + block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS); + l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4); + block |= (u64) l << 32; + printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block); + + if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP) + return; + bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR); + l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4); + bar |= (u64) l << 32; + printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar)); + if (PCI_MCAST_OVL_SIZE(bar) >= 6) + printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar)); + else + printf("(disabled)"); + printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK); +} + static void cap_vc(struct device *d, int where) { @@ -547,6 +634,57 @@ cap_rclink(struct device *d, int where) } } +static void +cap_dvsec_cxl(struct device *d, int where) +{ + u16 l; + + printf(": CXL\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_CXL_CAP, 12)) + return; + + l = get_conf_word(d, where + PCI_CXL_CAP); + printf("\t\tCXLCap:\tCache%c IO%c Mem%c Mem HW Init%c HDMCount %d Viral%c\n", + FLAG(l, PCI_CXL_CAP_CACHE), FLAG(l, PCI_CXL_CAP_IO), FLAG(l, PCI_CXL_CAP_MEM), + FLAG(l, PCI_CXL_CAP_MEM_HWINIT), PCI_CXL_CAP_HDM_CNT(l), FLAG(l, PCI_CXL_CAP_VIRAL)); + + l = get_conf_word(d, where + PCI_CXL_CTRL); + printf("\t\tCXLCtl:\tCache%c IO%c Mem%c Cache SF Cov %d Cache SF Gran %d Cache Clean%c Viral%c\n", + FLAG(l, PCI_CXL_CTRL_CACHE), FLAG(l, PCI_CXL_CTRL_IO), FLAG(l, PCI_CXL_CTRL_MEM), + PCI_CXL_CTRL_CACHE_SF_COV(l), PCI_CXL_CTRL_CACHE_SF_GRAN(l), FLAG(l, PCI_CXL_CTRL_CACHE_CLN), + FLAG(l, PCI_CXL_CTRL_VIRAL)); + + l = get_conf_word(d, where + PCI_CXL_STATUS); + printf("\t\tCXLSta:\tViral%c\n", FLAG(l, PCI_CXL_STATUS_VIRAL)); +} + +static void +cap_dvsec(struct device *d, int where) +{ + printf("Designated Vendor-Specific: "); + if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8)) + { + printf("\n"); + return; + } + + u32 hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1); + u16 vendor = BITS(hdr, 0, 16); + byte rev = BITS(hdr, 16, 4); + u16 len = BITS(hdr, 20, 12); + + u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2); + + printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len); + if (vendor == PCI_DVSEC_VENDOR_ID_CXL && id == PCI_DVSEC_ID_CXL && len >= 16) + cap_dvsec_cxl(d, where); + else + printf(" \n"); +} + static void cap_evendor(struct device *d, int where) { @@ -624,17 +762,19 @@ cap_l1pm(struct device *d, int where) FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11)); if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) - printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8)); - - if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) { - scale = BITS(val, 29, 3); - if (scale > 5) - printf(" LTR1.2_Threshold="); - else - printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale)); + printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8)); + + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + { + scale = BITS(val, 29, 3); + if (scale > 5) + printf(" LTR1.2_Threshold="); + else + printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale)); + } + printf("\n"); } - printf("\n"); val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2); printf("\t\tL1SubCtl2:"); @@ -708,6 +848,134 @@ cap_ptm(struct device *d, int where) } } +static void +print_rebar_range_size(int ld2_size) +{ + // This function prints the input as a power-of-2 size value + // It is biased with 1MB = 0, ... + // Maximum resizable BAR value supported is 2^63 bytes = 43 + // for the extended resizable BAR capability definition + // (otherwise it would stop at 2^28) + + if (ld2_size >= 0 && ld2_size < 10) + printf(" %dMB", (1 << ld2_size)); + else if (ld2_size >= 10 && ld2_size < 20) + printf(" %dGB", (1 << (ld2_size-10))); + else if (ld2_size >= 20 && ld2_size < 30) + printf(" %dTB", (1 << (ld2_size-20))); + else if (ld2_size >= 30 && ld2_size < 40) + printf(" %dPB", (1 << (ld2_size-30))); + else if (ld2_size >= 40 && ld2_size < 44) + printf(" %dEB", (1 << (ld2_size-40))); + else + printf(" "); +} + +static void +cap_rebar(struct device *d, int where, int virtual) +{ + u32 sizes_buffer, control_buffer, ext_sizes, current_size; + u16 bar_index, barcount, data_count; + // If structure exists at least one bar is defined + u16 num_bars = 1; + + printf("%s Resizable BAR\n", (virtual) ? "Virtual" : "Physical"); + + if (verbose < 1) + return; + + // Go through all defined BAR definitions of the caps, at minimum 1 + // (loop also terminates if num_bars read from caps is > 6) + for (barcount = 0; barcount < num_bars; barcount++) + { + where += 4; + + // Get the next BAR configuration + if (!config_fetch(d, where, 8)) + { + printf("\t\t\n"); + return; + } + + sizes_buffer = get_conf_long(d, where) >> 4; + + where += 4; + + control_buffer = get_conf_long(d, where); + + bar_index = control_buffer & 0x07; + current_size = (control_buffer >> 8) & 0x3f; + ext_sizes = control_buffer >> 16; + + if (barcount == 0) + { + // Only index 0 controlreg has the num_bar count definition + num_bars = (control_buffer >> 5) & 0x07; + if (verbose == 1) + { + // Must be below or equal 6 + if (num_bars <= 6) + { + // Fewer resizable BARs than total supported BARs may be available, + // or the resizable BAR support may not start at BAR index 0. + // list how many resizable BARs are expected. + printf("\t\t%d resizable BAR%s available\n", num_bars, (num_bars == 1) ? "" : "s"); + } + } + // If num_bars value is outside of the supported range, exit the parsing loop + if (num_bars > 6) + { + printf("\t\t", num_bars); + break; + } + } + + // Resizable BAR list entry have an arbitrary index and current size + printf("\t\tBAR %d, current size:", bar_index); + print_rebar_range_size(current_size); + + // Only print out the detail BAR sizes if vv is defined. Function modifies caps bits + // to enumerate supported sizes, ext_sizes is only != 0 for devices with + // extended resizable BAR capability, e.g. when > 128TB is needed + + if ((verbose < 2) || + ((sizes_buffer == 0) && (ext_sizes == 0))) + { + printf("\n"); + continue; + } + + printf("\n\t\tsupported:"); + + for (data_count = 0; data_count < 28; data_count++) + { + if ((sizes_buffer & (1U << data_count)) != 0) + { + // Mark the supported size as processed + sizes_buffer &= ~(1U << data_count); + print_rebar_range_size(data_count); + } + } + + // If a device needs > 128TB BAR, extended Resizable BAR feature is active and + // ext_sizes is set. This is not common. + + if (ext_sizes != 0) + { + for (data_count = 0; data_count < 16; data_count++) + { + if ((ext_sizes & (1U << data_count)) != 0) + { + // Mark the supported size as processed + ext_sizes &= ~(1U << data_count); + print_rebar_range_size((data_count + 28)); + } + } + } + printf("\n"); + } +} + void show_ext_caps(struct device *d, int type) { @@ -737,6 +1005,9 @@ show_ext_caps(struct device *d, int type) } switch (id) { + case PCI_EXT_CAP_ID_NULL: + printf("Null\n"); + break; case PCI_EXT_CAP_ID_AER: cap_aer(d, where, type); break; @@ -765,8 +1036,8 @@ show_ext_caps(struct device *d, int type) case PCI_EXT_CAP_ID_MFVC: printf("Multi-Function Virtual Channel \n"); break; - case PCI_EXT_CAP_ID_RBCB: - printf("Root Bridge Control Block \n"); + case PCI_EXT_CAP_ID_RCRB: + printf("Root Complex Register Block \n"); break; case PCI_EXT_CAP_ID_VNDR: cap_evendor(d, where); @@ -783,26 +1054,77 @@ show_ext_caps(struct device *d, int type) case PCI_EXT_CAP_ID_SRIOV: cap_sriov(d, where); break; + case PCI_EXT_CAP_ID_MRIOV: + printf("Multi-Root I/O Virtualization \n"); + break; + case PCI_EXT_CAP_ID_MCAST: + cap_multicast(d, where, type); + break; case PCI_EXT_CAP_ID_PRI: cap_pri(d, where); break; + case PCI_EXT_CAP_ID_REBAR: + cap_rebar(d, where, 0); + break; + case PCI_EXT_CAP_ID_DPA: + printf("Dynamic Power Allocation \n"); + break; case PCI_EXT_CAP_ID_TPH: cap_tph(d, where); break; case PCI_EXT_CAP_ID_LTR: cap_ltr(d, where); break; + case PCI_EXT_CAP_ID_SECPCI: + cap_sec(d, where); + break; + case PCI_EXT_CAP_ID_PMUX: + printf("Protocol Multiplexing \n"); + break; case PCI_EXT_CAP_ID_PASID: cap_pasid(d, where); break; + case PCI_EXT_CAP_ID_LNR: + printf("LN Requester \n"); + break; case PCI_EXT_CAP_ID_L1PM: cap_l1pm(d, where); break; case PCI_EXT_CAP_ID_PTM: cap_ptm(d, where); break; + case PCI_EXT_CAP_ID_M_PCIE: + printf("PCI Express over M_PHY \n"); + break; + case PCI_EXT_CAP_ID_FRS: + printf("FRS Queueing \n"); + break; + case PCI_EXT_CAP_ID_RTR: + printf("Readiness Time Reporting \n"); + break; + case PCI_EXT_CAP_ID_DVSEC: + cap_dvsec(d, where); + break; + case PCI_EXT_CAP_ID_VF_REBAR: + cap_rebar(d, where, 1); + break; + case PCI_EXT_CAP_ID_DLNK: + printf("Data Link Feature \n"); + break; + case PCI_EXT_CAP_ID_16GT: + printf("Physical Layer 16.0 GT/s \n"); + break; + case PCI_EXT_CAP_ID_LMR: + printf("Lane Margining at the Receiver \n"); + break; + case PCI_EXT_CAP_ID_HIER_ID: + printf("Hierarchy ID \n"); + break; + case PCI_EXT_CAP_ID_NPEM: + printf("Native PCIe Enclosure Management \n"); + break; default: - printf("#%02x\n", id); + printf("Extended Capability ID %#02x\n", id); break; } where = (header >> 20) & ~3;