X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=ls-ecaps.c;h=c6f217eb63d6691a36fa07ff61849726aaa21cbe;hb=c4a1aff42255ccac78c036d7f98a371039a0eede;hp=ed10f72be2628512c44bff961da71b41c9f562a1;hpb=d676f20d8161b7be7347b6990f6064fa3b171900;p=pciutils.git diff --git a/ls-ecaps.c b/ls-ecaps.c index ed10f72..c6f217e 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -11,6 +11,71 @@ #include "lspci.h" +static void +cap_tph(struct device *d, int where) +{ + u32 tph_cap; + printf("Transaction Processing Hints\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4)) + return; + + tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES); + + if (tph_cap & PCI_TPH_INTVEC_SUP) + printf("\t\tInterrupt vector mode supported\n"); + if (tph_cap & PCI_TPH_DEV_SUP) + printf("\t\tDevice specific mode supported\n"); + if (tph_cap & PCI_TPH_EXT_REQ_SUP) + printf("\t\tExtended requester support\n"); + + switch (tph_cap & PCI_TPH_ST_LOC_MASK) { + case PCI_TPH_ST_NONE: + printf("\t\tNo steering table available\n"); + break; + case PCI_TPH_ST_CAP: + printf("\t\tSteering table in TPH capability structure\n"); + break; + case PCI_TPH_ST_MSIX: + printf("\t\tSteering table in MSI-X table\n"); + break; + default: + printf("\t\tReserved steering table location\n"); + break; + } +} + +static u32 +cap_ltr_scale(u8 scale) +{ + return 1 << (scale * 5); +} + +static void +cap_ltr(struct device *d, int where) +{ + u32 scale; + u16 snoop, nosnoop; + printf("Latency Tolerance Reporting\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4)) + return; + + snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP); + scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); + printf("\t\tMax snoop latency: %lldns\n", + ((unsigned long long)snoop & PCI_LTR_VALUE_MASK) * scale); + + nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP); + scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); + printf("\t\tMax no snoop latency: %lldns\n", + ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale); +} + static void cap_dsn(struct device *d, int where) { @@ -274,7 +339,7 @@ cap_vc(struct device *d, int where) } rcap = get_conf_long(d, pos); rctrl = get_conf_long(d, pos+4); - rstatus = get_conf_word(d, pos+8); + rstatus = get_conf_word(d, pos+10); pat_pos = BITS(rcap, 24, 8); printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n", @@ -383,6 +448,58 @@ cap_evendor(struct device *d, int where) BITS(hdr, 20, 12)); } +static void +cap_l1pm(struct device *d, int where) +{ + u32 l1_cap; + int power_on_scale; + + printf("L1 PM Substates\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + 4, 4)) + { + printf("\t\t\n"); + return; + } + + l1_cap = get_conf_long(d, where + 4); + printf("\t\tL1SubCap: "); + printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n", + FLAG(l1_cap, 1), + FLAG(l1_cap, 2), + FLAG(l1_cap, 4), + FLAG(l1_cap, 8), + FLAG(l1_cap, 16)); + + if (BITS(l1_cap, 0, 1) || BITS(l1_cap, 2, 1)) + { + printf("\t\t\t PortCommonModeRestoreTime=%dus ", + BITS(l1_cap, 8,8)); + + power_on_scale = BITS(l1_cap, 16, 2); + + printf("PortTPowerOnTime="); + switch (power_on_scale) + { + case 0: + printf("%dus\n", BITS(l1_cap, 19, 5) * 2); + break; + case 1: + printf("%dus\n", BITS(l1_cap, 19, 5) * 10); + break; + case 2: + printf("%dus\n", BITS(l1_cap, 19, 5) * 100); + break; + default: + printf("\n"); + break; + } + } +} + void show_ext_caps(struct device *d) { @@ -455,6 +572,15 @@ show_ext_caps(struct device *d) case PCI_EXT_CAP_ID_SRIOV: cap_sriov(d, where); break; + case PCI_EXT_CAP_ID_TPH: + cap_tph(d, where); + break; + case PCI_EXT_CAP_ID_LTR: + cap_ltr(d, where); + break; + case PCI_EXT_CAP_ID_L1PM: + cap_l1pm(d, where); + break; default: printf("#%02x\n", id); break;