X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=ls-ecaps.c;h=634db21dd1b239ae0c408727bc5136ef0240b66e;hb=d9b1b8e350adbaf97713ce50b044f1c63d6a98cf;hp=fa3545f95d21ca063480c147b3e2a137e8e1b216;hpb=3edae14ac2590c1e35c8c746467015a19be5d2e9;p=pciutils.git diff --git a/ls-ecaps.c b/ls-ecaps.c index fa3545f..634db21 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -11,6 +11,71 @@ #include "lspci.h" +static void +cap_tph(struct device *d, int where) +{ + u32 tph_cap; + printf("Transaction Processing Hints\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4)) + return; + + tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES); + + if (tph_cap & PCI_TPH_INTVEC_SUP) + printf("\t\tInterrupt vector mode supported\n"); + if (tph_cap & PCI_TPH_DEV_SUP) + printf("\t\tDevice specific mode supported\n"); + if (tph_cap & PCI_TPH_EXT_REQ_SUP) + printf("\t\tExtended requester support\n"); + + switch (tph_cap & PCI_TPH_ST_LOC_MASK) { + case PCI_TPH_ST_NONE: + printf("\t\tNo steering table available\n"); + break; + case PCI_TPH_ST_CAP: + printf("\t\tSteering table in TPH capability structure\n"); + break; + case PCI_TPH_ST_MSIX: + printf("\t\tSteering table in MSI-X table\n"); + break; + default: + printf("\t\tReserved steering table location\n"); + break; + } +} + +static u32 +cap_ltr_scale(u8 scale) +{ + return 1 << (scale * 5); +} + +static void +cap_ltr(struct device *d, int where) +{ + u32 scale; + u16 snoop, nosnoop; + printf("Latency Tolerance Reporting\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4)) + return; + + snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP); + scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); + printf("\t\tMax snoop latency: %lldns\n", + ((unsigned long long)snoop & PCI_LTR_VALUE_MASK) * scale); + + nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP); + scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); + printf("\t\tMax no snoop latency: %lldns\n", + ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale); +} + static void cap_dsn(struct device *d, int where) { @@ -25,15 +90,16 @@ cap_dsn(struct device *d, int where) } static void -cap_aer(struct device *d, int where) +cap_aer(struct device *d, int where, int type) { - u32 l; + u32 l, l0, l1, l2, l3; + u16 w; printf("Advanced Error Reporting\n"); if (verbose < 2) return; - if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24)) + if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40)) return; l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS); @@ -66,10 +132,79 @@ cap_aer(struct device *d, int where) FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE)); l = get_conf_long(d, where + PCI_ERR_CAP); - printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n", + printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n" + "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n", PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE), - FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE)); + FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE), + FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE), + FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG)); + + l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG); + l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4); + l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8); + l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12); + printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3); + + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) + { + if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12)) + return; + + l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND); + printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n", + FLAG(l, PCI_ERR_ROOT_CMD_COR_EN), + FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN), + FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN)); + + l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS); + printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n" + "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n", + FLAG(l, PCI_ERR_ROOT_COR_RCV), + FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV), + FLAG(l, PCI_ERR_ROOT_UNCOR_RCV), + FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV), + FLAG(l, PCI_ERR_ROOT_FIRST_FATAL), + FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV), + FLAG(l, PCI_ERR_ROOT_FATAL_RCV), + PCI_ERR_MSG_NUM(l)); + + w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC); + printf("\t\tErrorSrc: ERR_COR: %04x ", w); + + w = get_conf_word(d, where + PCI_ERR_ROOT_SRC); + printf("ERR_FATAL/NONFATAL: %04x\n", w); + } +} + +static void cap_dpc(struct device *d, int where) +{ + u16 l; + printf("Downstream Port Containment\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_DPC_CAP, 8)) + return; + + l = get_conf_word(d, where + PCI_DPC_CAP); + printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", + PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK), + FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR)); + + l = get_conf_word(d, where + PCI_DPC_CTL); + printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n", + PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT), + FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER), + FLAG(l, PCI_DPC_CTL_DL_ACTIVE)); + + l = get_conf_word(d, where + PCI_DPC_STATUS); + printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n", + FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT), + FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l)); + + l = get_conf_word(d, where + PCI_DPC_SOURCE); + printf("\t\tSource:\t%04x\n", l); } static void @@ -139,6 +274,54 @@ cap_ats(struct device *d, int where) FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w)); } +static void +cap_pri(struct device *d, int where) +{ + u16 w; + u32 l; + + printf("Page Request Interface (PRI)\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc)) + return; + + w = get_conf_word(d, where + PCI_PRI_CTRL); + printf("\t\tPRICtl: Enable%c Reset%c\n", + FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET)); + w = get_conf_word(d, where + PCI_PRI_STATUS); + printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n", + FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI), + FLAG(w, PCI_PRI_STATUS_STOPPED)); + l = get_conf_long(d, where + PCI_PRI_MAX_REQ); + printf("\t\tPage Request Capacity: %08x, ", l); + l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ); + printf("Page Request Allocation: %08x\n", l); +} + +static void +cap_pasid(struct device *d, int where) +{ + u16 w; + + printf("Process Address Space ID (PASID)\n"); + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_PASID_CAP, 4)) + return; + + w = get_conf_word(d, where + PCI_PASID_CAP); + printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n", + FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV), + PCI_PASID_CAP_WIDTH(w)); + w = get_conf_word(d, where + PCI_PASID_CTRL); + printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n", + FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC), + FLAG(w, PCI_PASID_CTRL_PRIV)); +} + static void cap_sriov(struct device *d, int where) { @@ -239,23 +422,25 @@ cap_vc(struct device *d, int where) status = get_conf_word(d, where + PCI_VC_PORT_STATUS); evc_cnt = BITS(cr1, 0, 3); - printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntrySize=%d\n", + printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n", BITS(cr1, 4, 3), TABLE(ref_clocks, BITS(cr1, 8, 2), buf), - BITS(cr1, 10, 2)); + 1 << BITS(cr1, 10, 2)); - printf("\t\tArb:\t"); + printf("\t\tArb:"); for (i=0; i<8; i++) if (arb_selects[i][0] != '?' || cr2 & (1 << i)) - printf("%s%c ", arb_selects[i], FLAG(cr2, 1 << i)); + printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i)); arb_table_pos = BITS(cr2, 24, 8); - printf("TableOffset=%x\n", arb_table_pos); - printf("\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf)); + printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf)); printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1)); if (arb_table_pos) - printf("\t\tPort Arbitration Table \n"); + { + arb_table_pos = where + 16*arb_table_pos; + printf("\t\tPort Arbitration Table [%x] \n", arb_table_pos); + } for (i=0; i<=evc_cnt; i++) { @@ -272,7 +457,7 @@ cap_vc(struct device *d, int where) } rcap = get_conf_long(d, pos); rctrl = get_conf_long(d, pos+4); - rstatus = get_conf_word(d, pos+8); + rstatus = get_conf_word(d, pos+10); pat_pos = BITS(rcap, 24, 8); printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n", @@ -381,8 +566,150 @@ cap_evendor(struct device *d, int where) BITS(hdr, 20, 12)); } +static int l1pm_calc_pwron(int scale, int value) +{ + switch (scale) + { + case 0: + return 2 * value; + case 1: + return 10 * value; + case 2: + return 100 * value; + } + return -1; +} + +static void +cap_l1pm(struct device *d, int where) +{ + u32 l1_cap, val, scale; + int time; + + printf("L1 PM Substates\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12)) + { + printf("\t\t\n"); + return; + } + + l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP); + printf("\t\tL1SubCap: "); + printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n", + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP)); + + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + { + printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8)); + time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5)); + if (time != -1) + printf("PortTPowerOnTime=%dus\n", time); + else + printf("PortTPowerOnTime=\n"); + } + + val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1); + printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n", + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12), + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11), + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12), + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11)); + + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8)); + + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + { + scale = BITS(val, 29, 3); + if (scale > 5) + printf(" LTR1.2_Threshold="); + else + printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale)); + } + printf("\n"); + + val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2); + printf("\t\tL1SubCtl2:"); + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + { + time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5)); + if (time != -1) + printf(" T_PwrOn=%dus", time); + else + printf(" T_PwrOn="); + } + printf("\n"); +} + +static void +cap_ptm(struct device *d, int where) +{ + u32 buff; + u16 clock; + + printf("Precision Time Measurement\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + 4, 8)) + { + printf("\t\t\n"); + return; + } + + buff = get_conf_long(d, where + 4); + printf("\t\tPTMCap: "); + printf("Requester:%c Responder:%c Root:%c\n", + FLAG(buff, 0x1), + FLAG(buff, 0x2), + FLAG(buff, 0x4)); + + clock = BITS(buff, 8, 8); + printf("\t\tPTMClockGranularity: "); + switch (clock) + { + case 0x00: + printf("Unimplemented\n"); + break; + case 0xff: + printf("Greater than 254ns\n"); + break; + default: + printf("%huns\n", clock); + } + + buff = get_conf_long(d, where + 8); + printf("\t\tPTMControl: "); + printf("Enabled:%c RootSelected:%c\n", + FLAG(buff, 0x1), + FLAG(buff, 0x2)); + + clock = BITS(buff, 8, 8); + printf("\t\tPTMEffectiveGranularity: "); + switch (clock) + { + case 0x00: + printf("Unknown\n"); + break; + case 0xff: + printf("Greater than 254ns\n"); + break; + default: + printf("%huns\n", clock); + } +} + void -show_ext_caps(struct device *d) +show_ext_caps(struct device *d, int type) { int where = 0x100; char been_there[0x1000]; @@ -411,7 +738,10 @@ show_ext_caps(struct device *d) switch (id) { case PCI_EXT_CAP_ID_AER: - cap_aer(d, where); + cap_aer(d, where, type); + break; + case PCI_EXT_CAP_ID_DPC: + cap_dpc(d, where); break; case PCI_EXT_CAP_ID_VC: case PCI_EXT_CAP_ID_VC2: @@ -453,6 +783,24 @@ show_ext_caps(struct device *d) case PCI_EXT_CAP_ID_SRIOV: cap_sriov(d, where); break; + case PCI_EXT_CAP_ID_PRI: + cap_pri(d, where); + break; + case PCI_EXT_CAP_ID_TPH: + cap_tph(d, where); + break; + case PCI_EXT_CAP_ID_LTR: + cap_ltr(d, where); + break; + case PCI_EXT_CAP_ID_PASID: + cap_pasid(d, where); + break; + case PCI_EXT_CAP_ID_L1PM: + cap_l1pm(d, where); + break; + case PCI_EXT_CAP_ID_PTM: + cap_ptm(d, where); + break; default: printf("#%02x\n", id); break;