X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=ls-ecaps.c;h=4417cd9e1824bd552d4948214f5b289686b2a60c;hb=6469d596a8b3c4e0eba1495a74788d5e80751da8;hp=eae3a3d40a6053f862e9bf6c98fc31ff2e4acac5;hpb=a1492b88709ee5a1565d82eee0387a42625caeac;p=pciutils.git

diff --git a/ls-ecaps.c b/ls-ecaps.c
index eae3a3d..4417cd9 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -76,6 +76,37 @@ cap_ltr(struct device *d, int where)
 	 ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale);
 }
 
+static void
+cap_sec(struct device *d, int where, int type)
+{
+  u32 ctrl3, lane_err_stat;
+  u8 lane;
+  printf("Secondary PCI Express\n");
+  if (verbose < 2 && type == 0)
+    return;
+
+  if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12))
+    return;
+
+  ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3);
+  printf("\t\tLnkCtl3: LnkEquIntrruptEn%c, PerformEqu%c\n",
+	FLAG(ctrl3, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN),
+	FLAG(ctrl3, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU));
+
+  lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR);
+  printf("\t\tLaneErrStat: ");
+  if (lane_err_stat)
+    {
+      printf("LaneErr at lane:");
+      for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1)
+        if (BITS(lane_err_stat, 0, 1))
+          printf(" %u", lane);
+    }
+  else
+    printf("0");
+  printf("\n");
+}
+
 static void
 cap_dsn(struct device *d, int where)
 {
@@ -124,15 +155,15 @@ cap_aer(struct device *d, int where, int type)
 	FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
 	FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
   l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
-  printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
+  printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
 	FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
 	FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
   l = get_conf_long(d, where + PCI_ERR_COR_MASK);
-  printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
+  printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
 	FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
 	FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
   l = get_conf_long(d, where + PCI_ERR_CAP);
-  printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n"
+  printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
 	"\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
 	PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
 	FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
@@ -396,6 +427,62 @@ cap_sriov(struct device *d, int where)
 	PCI_IOV_MSA_BIR(l));
 }
 
+static void
+cap_multicast(struct device *d, int where, int type)
+{
+  u16 w;
+  u32 l;
+  u64 bar, rcv, block;
+
+  printf("Multicast\n");
+  if (verbose < 2)
+    return;
+
+  if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30))
+    return;
+
+  w = get_conf_word(d, where + PCI_MCAST_CAP);
+  printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1);
+  if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
+    printf(", WindowSz %d (%d bytes)",
+      PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w));
+  if (type == PCI_EXP_TYPE_ROOT_PORT ||
+      type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM)
+    printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC));
+  w = get_conf_word(d, where + PCI_MCAST_CTRL);
+  printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
+    PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE));
+  bar = get_conf_long(d, where + PCI_MCAST_BAR);
+  l = get_conf_long(d, where + PCI_MCAST_BAR + 4);
+  bar |= (u64) l << 32;
+  printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n",
+    PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK);
+  rcv = get_conf_long(d, where + PCI_MCAST_RCV);
+  l = get_conf_long(d, where + PCI_MCAST_RCV + 4);
+  rcv |= (u64) l << 32;
+  printf("\t\tMcastReceiveVec:      %016" PCI_U64_FMT_X "\n", rcv);
+  block = get_conf_long(d, where + PCI_MCAST_BLOCK);
+  l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4);
+  block |= (u64) l << 32;
+  printf("\t\tMcastBlockAllVec:     %016" PCI_U64_FMT_X "\n", block);
+  block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS);
+  l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4);
+  block |= (u64) l << 32;
+  printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block);
+
+  if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
+    return;
+  bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR);
+  l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4);
+  bar |= (u64) l << 32;
+  printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar));
+  if (PCI_MCAST_OVL_SIZE(bar) >= 6)
+    printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar));
+  else
+    printf("(disabled)");
+  printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK);
+}
+
 static void
 cap_vc(struct device *d, int where)
 {
@@ -624,17 +711,19 @@ cap_l1pm(struct device *d, int where)
     FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
 
   if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
-    printf("\t\t\t   T_CommonMode=%dus", BITS(val, 8, 8));
-
-  if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
     {
-      scale = BITS(val, 29, 3);
-      if (scale > 5)
-	printf(" LTR1.2_Threshold=<error>");
-      else
-	printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale));
+      printf("\t\t\t   T_CommonMode=%dus", BITS(val, 8, 8));
+
+      if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
+	{
+	  scale = BITS(val, 29, 3);
+	  if (scale > 5)
+	    printf(" LTR1.2_Threshold=<error>");
+	  else
+	    printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale));
+	}
+      printf("\n");
     }
-  printf("\n");
 
   val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
   printf("\t\tL1SubCtl2:");
@@ -737,6 +826,9 @@ show_ext_caps(struct device *d, int type)
 	}
       switch (id)
 	{
+	  case PCI_EXT_CAP_ID_NULL:
+	    printf("Null\n");
+	    break;
 	  case PCI_EXT_CAP_ID_AER:
 	    cap_aer(d, where, type);
 	    break;
@@ -765,8 +857,8 @@ show_ext_caps(struct device *d, int type)
 	  case PCI_EXT_CAP_ID_MFVC:
 	    printf("Multi-Function Virtual Channel <?>\n");
 	    break;
-	  case PCI_EXT_CAP_ID_RBCB:
-	    printf("Root Bridge Control Block <?>\n");
+	  case PCI_EXT_CAP_ID_RCRB:
+	    printf("Root Complex Register Block <?>\n");
 	    break;
 	  case PCI_EXT_CAP_ID_VNDR:
 	    cap_evendor(d, where);
@@ -783,26 +875,77 @@ show_ext_caps(struct device *d, int type)
 	  case PCI_EXT_CAP_ID_SRIOV:
 	    cap_sriov(d, where);
 	    break;
+	  case PCI_EXT_CAP_ID_MRIOV:
+	    printf("Multi-Root I/O Virtualization <?>\n");
+	    break;
+	  case PCI_EXT_CAP_ID_MCAST:
+	    cap_multicast(d, where, type);
+	    break;
 	  case PCI_EXT_CAP_ID_PRI:
 	    cap_pri(d, where);
 	    break;
+	  case PCI_EXT_CAP_ID_REBAR:
+	    printf("Resizable BAR <?>\n");
+	    break;
+	  case PCI_EXT_CAP_ID_DPA:
+	    printf("Dynamic Power Allocation <?>\n");
+	    break;
 	  case PCI_EXT_CAP_ID_TPH:
 	    cap_tph(d, where);
 	    break;
 	  case PCI_EXT_CAP_ID_LTR:
 	    cap_ltr(d, where);
 	    break;
+	  case PCI_EXT_CAP_ID_SECPCI:
+	    cap_sec(d, where, type);
+	    break;
+	  case PCI_EXT_CAP_ID_PMUX:
+	    printf("Protocol Multiplexing <?>\n");
+	    break;
 	  case PCI_EXT_CAP_ID_PASID:
 	    cap_pasid(d, where);
 	    break;
+	  case PCI_EXT_CAP_ID_LNR:
+	    printf("LN Requester <?>\n");
+	    break;
 	  case PCI_EXT_CAP_ID_L1PM:
 	    cap_l1pm(d, where);
 	    break;
 	  case PCI_EXT_CAP_ID_PTM:
 	    cap_ptm(d, where);
 	    break;
+	  case PCI_EXT_CAP_ID_M_PCIE:
+	    printf("PCI Express over M_PHY <?>\n");
+	    break;
+	  case PCI_EXT_CAP_ID_FRS:
+	    printf("FRS Queueing <?>\n");
+	    break;
+	  case PCI_EXT_CAP_ID_RTR:
+	    printf("Readiness Time Reporting <?>\n");
+	    break;
+	  case PCI_EXT_CAP_ID_DVSEC:
+	    printf("Designated Vendor-Specific <?>\n");
+	    break;
+	  case PCI_EXT_CAP_ID_VF_REBAR:
+	    printf("VF Resizable BAR <?>\n");
+	    break;
+	  case PCI_EXT_CAP_ID_DLNK:
+	    printf("Data Link Feature <?>\n");
+	    break;
+	  case PCI_EXT_CAP_ID_16GT:
+	    printf("Physical Layer 16.0 GT/s <?>\n");
+	    break;
+	  case PCI_EXT_CAP_ID_LMR:
+	    printf("Lane Margining at the Receiver <?>\n");
+	    break;
+	  case PCI_EXT_CAP_ID_HIER_ID:
+	    printf("Hierarchy ID <?>\n");
+	    break;
+	  case PCI_EXT_CAP_ID_NPEM:
+	    printf("Native PCIe Enclosure Management <?>\n");
+	    break;
 	  default:
-	    printf("#%02x\n", id);
+	    printf("Extended Capability ID %#02x\n", id);
 	    break;
 	}
       where = (header >> 20) & ~3;