X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=ls-caps.c;h=e74d13a8bac20b5d846076e7d7bf73ce6b1aee72;hb=0547ded87cb2757044d4bcbdcafce32fc14c860f;hp=de0d79e70f0284c103fc2d2946ab7c0f4537334c;hpb=77120d53649678ea1cb72591f522d63c27b6a261;p=pciutils.git diff --git a/ls-caps.c b/ls-caps.c index de0d79e..e74d13a 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -1,7 +1,7 @@ /* * The PCI Utilities -- Show Capabilities * - * Copyright (c) 1997--2010 Martin Mares + * Copyright (c) 1997--2018 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ @@ -25,7 +25,7 @@ cap_pm(struct device *d, int where, int cap) FLAG(cap, PCI_PM_CAP_DSI), FLAG(cap, PCI_PM_CAP_D1), FLAG(cap, PCI_PM_CAP_D2), - pm_aux_current[(cap >> 6) & 7], + pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6], FLAG(cap, PCI_PM_CAP_PME_D0), FLAG(cap, PCI_PM_CAP_PME_D1), FLAG(cap, PCI_PM_CAP_PME_D2), @@ -136,17 +136,17 @@ cap_pcix_nobridge(struct device *d, int where) 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)), max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]); printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n", - ((status >> 8) & 0xff), - ((status >> 3) & 0x1f), + (status & PCI_PCIX_STATUS_BUS) >> 8, + (status & PCI_PCIX_STATUS_DEVICE) >> 3, (status & PCI_PCIX_STATUS_FUNCTION), FLAG(status, PCI_PCIX_STATUS_64BIT), FLAG(status, PCI_PCIX_STATUS_133MHZ), FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED), FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC), ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"), - 1 << (9 + ((status >> 21) & 3U)), - max_outstanding[(status >> 23) & 7U], - 1 << (3 + ((status >> 26) & 7U)), + 1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)), + max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23], + 1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)), FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS), FLAG(status, PCI_PCIX_STATUS_266MHZ), FLAG(status, PCI_PCIX_STATUS_533MHZ)); @@ -175,11 +175,11 @@ cap_pcix_bridge(struct device *d, int where) FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC), FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN), FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED), - sec_clock_freq[(secstatus >> 6) & 7]); + sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]); status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS); printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n", - ((status >> 8) & 0xff), - ((status >> 3) & 0x1f), + (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8, + (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3, (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT), FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ), @@ -678,14 +678,15 @@ static void cap_express_dev(struct device *d, int where, int type) if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) printf(" FLReset%c", FLAG(t, PCI_EXP_DEVCAP_FLRESET)); - if (type == PCI_EXP_TYPE_UPSTREAM) + if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) || + (type == PCI_EXP_TYPE_PCI_BRIDGE)) printf(" SlotPowerLimit %.3fW", power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26)); printf("\n"); w = get_conf_word(d, where + PCI_EXP_DEVCTL); - printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n", + printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n", FLAG(w, PCI_EXP_DEVCTL_CERE), FLAG(w, PCI_EXP_DEVCTL_NFERE), FLAG(w, PCI_EXP_DEVCTL_FERE), @@ -706,7 +707,7 @@ static void cap_express_dev(struct device *d, int where, int type) 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12)); w = get_conf_word(d, where + PCI_EXP_DEVSTA); - printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n", + printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n", FLAG(w, PCI_EXP_DEVSTA_CED), FLAG(w, PCI_EXP_DEVSTA_NFED), FLAG(w, PCI_EXP_DEVSTA_FED), @@ -725,11 +726,22 @@ static char *link_speed(int speed) return "5GT/s"; case 3: return "8GT/s"; + case 4: + return "16GT/s"; default: return "unknown"; } } +static char *link_compare(int sta, int cap) +{ + if (sta < cap) + return "downgraded"; + if (sta > cap) + return "strange"; + return "ok"; +} + static char *aspm_support(int code) { switch (code) @@ -755,30 +767,41 @@ static const char *aspm_enabled(int code) static void cap_express_link(struct device *d, int where, int type) { - u32 t; + u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width; u16 w; t = get_conf_long(d, where + PCI_EXP_LNKCAP); - printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Exit Latency L0s %s, L1 %s\n", + aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10; + cap_speed = t & PCI_EXP_LNKCAP_SPEED; + cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4; + printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s", t >> 24, - link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4, - aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10), - latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12), - latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15)); - printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c\n", + link_speed(cap_speed), cap_width, + aspm_support(aspm)); + if (aspm) + { + printf(", Exit Latency "); + if (aspm & 1) + printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12)); + if (aspm & 2) + printf("%sL1 %s", (aspm & 1) ? ", " : "", + latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15)); + } + printf("\n"); + printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n", FLAG(t, PCI_EXP_LNKCAP_CLOCKPM), FLAG(t, PCI_EXP_LNKCAP_SURPRISE), FLAG(t, PCI_EXP_LNKCAP_DLLA), - FLAG(t, PCI_EXP_LNKCAP_LBNC)); + FLAG(t, PCI_EXP_LNKCAP_LBNC), + FLAG(t, PCI_EXP_LNKCAP_AOC)); w = get_conf_word(d, where + PCI_EXP_LNKCTL); printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM)); if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) || - (type == PCI_EXP_TYPE_LEG_END)) + (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE)) printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64); - printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n", + printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n", FLAG(w, PCI_EXP_LNKCTL_DISABLE), - FLAG(w, PCI_EXP_LNKCTL_RETRAIN), FLAG(w, PCI_EXP_LNKCTL_CLOCK), FLAG(w, PCI_EXP_LNKCTL_XSYNCH), FLAG(w, PCI_EXP_LNKCTL_CLOCKPM), @@ -787,9 +810,14 @@ static void cap_express_link(struct device *d, int where, int type) FLAG(w, PCI_EXP_LNKCTL_AUTBWIE)); w = get_conf_word(d, where + PCI_EXP_LNKSTA); - printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n", - link_speed(w & PCI_EXP_LNKSTA_SPEED), - (w & PCI_EXP_LNKSTA_WIDTH) >> 4, + sta_speed = w & PCI_EXP_LNKSTA_SPEED; + sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4; + printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n", + link_speed(sta_speed), + link_compare(sta_speed, cap_speed), + sta_width, + link_compare(sta_width, cap_width)); + printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n", FLAG(w, PCI_EXP_LNKSTA_TR_ERR), FLAG(w, PCI_EXP_LNKSTA_TRAIN), FLAG(w, PCI_EXP_LNKSTA_SL_CLK), @@ -819,7 +847,7 @@ static void cap_express_slot(struct device *d, int where) FLAG(t, PCI_EXP_SLTCAP_HPC), FLAG(t, PCI_EXP_SLTCAP_HPS)); printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n", - t >> 19, + (t & PCI_EXP_SLTCAP_PSN) >> 19, power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15), FLAG(t, PCI_EXP_SLTCAP_INTERLOCK), FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP)); @@ -867,7 +895,7 @@ static void cap_express_root(struct device *d, int where) printf("\t\tRootCap: CRSVisible%c\n", FLAG(w, PCI_EXP_RTCAP_CRSVIS)); - w = get_conf_word(d, where + PCI_EXP_RTSTA); + w = get_conf_long(d, where + PCI_EXP_RTSTA); printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n", w & PCI_EXP_RTSTA_PME_REQID, FLAG(w, PCI_EXP_RTSTA_PME_STATUS), @@ -960,10 +988,29 @@ static const char *cap_express_devctl2_obff(int obff) } } +static int +device_has_memory_space_bar(struct device *d) +{ + struct pci_dev *p = d->dev; + int i, found = 0; + + for (i=0; i<6; i++) + if (p->base_addr[i] && p->size[i]) + { + if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO)) + { + found = 1; + break; + } + } + return found; +} + static void cap_express_dev2(struct device *d, int where, int type) { u32 l; u16 w; + int has_mem_bar = device_has_memory_space_bar(d); l = get_conf_long(d, where + PCI_EXP_DEVCAP2); printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s", @@ -975,6 +1022,20 @@ static void cap_express_dev2(struct device *d, int where, int type) printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI)); else printf("\n"); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || + type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar) + { + printf("\t\t\t AtomicOpsCap:"); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || + type == PCI_EXP_TYPE_DOWNSTREAM) + printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING)); + if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar) + printf(" 32bit%c 64bit%c 128bitCAS%c", + FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP), + FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP), + FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP)); + printf("\n"); + } w = get_conf_word(d, where + PCI_EXP_DEVCTL2); printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s", @@ -986,6 +1047,19 @@ static void cap_express_dev2(struct device *d, int where, int type) printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI)); else printf("\n"); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || + type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT || + type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END) + { + printf("\t\t\t AtomicOpsCtl:"); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT || + type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END) + printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN)); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || + type == PCI_EXP_TYPE_DOWNSTREAM) + printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK)); + printf("\n"); + } } static const char *cap_express_link2_speed(int type) @@ -999,6 +1073,8 @@ static const char *cap_express_link2_speed(int type) return "5GT/s"; case 3: return "8GT/s"; + case 4: + return "16GT/s"; default: return "Unknown"; } @@ -1074,7 +1150,7 @@ static void cap_express_slot2(struct device *d UNUSED, int where UNUSED) /* No capabilities that require this field in PCIe rev2.0 spec. */ } -static void +static int cap_express(struct device *d, int where, int cap) { int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4; @@ -1108,7 +1184,9 @@ cap_express(struct device *d, int where, int cap) printf("PCI-Express to PCI/PCI-X Bridge"); break; case PCI_EXP_TYPE_PCIE_BRIDGE: - printf("PCI/PCI-X to PCI-Express Bridge"); + slot = cap & PCI_EXP_FLAGS_SLOT; + printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)", + FLAG(cap, PCI_EXP_FLAGS_SLOT)); break; case PCI_EXP_TYPE_ROOT_INT_EP: link = 0; @@ -1123,7 +1201,7 @@ cap_express(struct device *d, int where, int cap) } printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9); if (verbose < 2) - return; + return type; size = 16; if (slot) @@ -1131,7 +1209,7 @@ cap_express(struct device *d, int where, int cap) if (type == PCI_EXP_TYPE_ROOT_PORT) size = 32; if (!config_fetch(d, where + PCI_EXP_DEVCAP, size)) - return; + return type; cap_express_dev(d, where, type); if (link) @@ -1142,19 +1220,20 @@ cap_express(struct device *d, int where, int cap) cap_express_root(d, where); if ((cap & PCI_EXP_FLAGS_VERS) < 2) - return; + return type; size = 16; if (slot) size = 24; if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size)) - return; + return type; cap_express_dev2(d, where, type); if (link) cap_express_link2(d, where, type); if (slot) cap_express_slot2(d, where); + return type; } static void @@ -1254,15 +1333,169 @@ cap_sata_hba(struct device *d, int where, int cap) printf(" BAR??%d\n", bar); } +static const char *cap_ea_property(int p, int is_secondary) +{ + switch (p) { + case 0x00: + return "memory space, non-prefetchable"; + case 0x01: + return "memory space, prefetchable"; + case 0x02: + return "I/O space"; + case 0x03: + return "VF memory space, prefetchable"; + case 0x04: + return "VF memory space, non-prefetchable"; + case 0x05: + return "allocation behind bridge, non-prefetchable memory"; + case 0x06: + return "allocation behind bridge, prefetchable memory"; + case 0x07: + return "allocation behind bridge, I/O space"; + case 0xfd: + return "memory space resource unavailable for use"; + case 0xfe: + return "I/O space resource unavailable for use"; + case 0xff: + if (is_secondary) + return "entry unavailable for use, PrimaryProperties should be used"; + else + return "entry unavailable for use"; + default: + return NULL; + } +} + +static void cap_ea(struct device *d, int where, int cap) +{ + int entry; + int entry_base = where + 4; + int num_entries = BITS(cap, 0, 6); + u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f; + + printf("Enhanced Allocation (EA): NumEntries=%u", num_entries); + if (htype == PCI_HEADER_TYPE_BRIDGE) { + byte fixed_sub, fixed_sec; + + entry_base += 4; + if (!config_fetch(d, where + 4, 2)) { + printf("\n"); + return; + } + fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY); + fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE); + printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub); + } + printf("\n"); + if (verbose < 2) + return; + + for (entry = 0; entry < num_entries; entry++) { + int max_offset_high_pos, has_base_high, has_max_offset_high; + u32 entry_header; + u32 base, max_offset; + int es, bei, pp, sp; + const char *prop_text; + + if (!config_fetch(d, entry_base, 4)) + return; + entry_header = get_conf_long(d, entry_base); + es = BITS(entry_header, 0, 3); + bei = BITS(entry_header, 4, 4); + pp = BITS(entry_header, 8, 8); + sp = BITS(entry_header, 16, 8); + if (!config_fetch(d, entry_base + 4, es * 4)) + return; + printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry, + FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE), + FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es); + printf("\t\t\t BAR Equivalent Indicator: "); + switch (bei) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + printf("BAR %u", bei); + break; + case 6: + printf("resource behind function"); + break; + case 7: + printf("not indicated"); + break; + case 8: + printf("expansion ROM"); + break; + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + printf("VF-BAR %u", bei - 9); + break; + default: + printf("reserved"); + break; + } + printf("\n"); + + prop_text = cap_ea_property(pp, 0); + printf("\t\t\t PrimaryProperties: "); + if (prop_text) + printf("%s\n", prop_text); + else + printf("[%02x]\n", pp); + + prop_text = cap_ea_property(sp, 1); + printf("\t\t\t SecondaryProperties: "); + if (prop_text) + printf("%s\n", prop_text); + else + printf("[%02x]\n", sp); + + base = get_conf_long(d, entry_base + 4); + has_base_high = ((base & 2) != 0); + base &= ~3; + + max_offset = get_conf_long(d, entry_base + 8); + has_max_offset_high = ((max_offset & 2) != 0); + max_offset |= 3; + max_offset_high_pos = entry_base + 12; + + printf("\t\t\t Base: "); + if (has_base_high) { + u32 base_high = get_conf_long(d, entry_base + 12); + + printf("%x", base_high); + max_offset_high_pos += 4; + } + printf("%08x\n", base); + + printf("\t\t\t MaxOffset: "); + if (has_max_offset_high) { + u32 max_offset_high = get_conf_long(d, max_offset_high_pos); + + printf("%x", max_offset_high); + } + printf("%08x\n", max_offset); + + entry_base += 4 + 4 * es; + } +} + void show_caps(struct device *d, int where) { int can_have_ext_caps = 0; + int type = -1; if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST) { - where = get_conf_byte(d, where) & ~3; byte been_there[256]; + where = get_conf_byte(d, where) & ~3; memset(been_there, 0, 256); while (where) { @@ -1315,7 +1548,7 @@ show_caps(struct device *d, int where) cap_ht(d, where, cap); break; case PCI_CAP_ID_VNDR: - printf("Vendor Specific Information: Len=%02x \n", BITS(cap, 0, 8)); + show_vendor_caps(d, where, cap); break; case PCI_CAP_ID_DBG: cap_debug_port(cap); @@ -1336,7 +1569,7 @@ show_caps(struct device *d, int where) printf("Secure device \n"); break; case PCI_CAP_ID_EXP: - cap_express(d, where, cap); + type = cap_express(d, where, cap); can_have_ext_caps = 1; break; case PCI_CAP_ID_MSIX: @@ -1348,6 +1581,9 @@ show_caps(struct device *d, int where) case PCI_CAP_ID_AF: cap_af(d, where); break; + case PCI_CAP_ID_EA: + cap_ea(d, where, cap); + break; default: printf("#%02x [%04x]\n", id, cap); } @@ -1355,5 +1591,5 @@ show_caps(struct device *d, int where) } } if (can_have_ext_caps) - show_ext_caps(d); + show_ext_caps(d, type); }