X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=ls-caps.c;h=a09b0cf339ed6e7e756fbad4525f3558c15b2461;hb=8b122188dfd404984eb360e8d876682fe7eb1613;hp=d4aebc8e80753d9319923fbf8d25fd5c8e2e3e8f;hpb=23c277980bb711eebfd588783509c6b9d5cc8507;p=pciutils.git diff --git a/ls-caps.c b/ls-caps.c index d4aebc8..a09b0cf 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -1,7 +1,7 @@ /* * The PCI Utilities -- Show Capabilities * - * Copyright (c) 1997--2010 Martin Mares + * Copyright (c) 1997--2018 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ @@ -231,7 +231,6 @@ cap_ht_pri(struct device *d, int where, int cmd) { u16 lctr0, lcnf0, lctr1, lcnf1, eh; u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn; - char *fmt; printf("HyperTransport: Slave or Primary Interface\n"); if (verbose < 2) @@ -243,22 +242,17 @@ cap_ht_pri(struct device *d, int where, int cmd) if (rid < 0x22 && rid > 0x11) printf("\t\t!!! Possibly incomplete decoding\n"); - if (rid >= 0x22) - fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n"; - else - fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n"; - printf(fmt, + printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c", (cmd & PCI_HT_PRI_CMD_BUID), (cmd & PCI_HT_PRI_CMD_UC) >> 5, FLAG(cmd, PCI_HT_PRI_CMD_MH), - FLAG(cmd, PCI_HT_PRI_CMD_DD), - FLAG(cmd, PCI_HT_PRI_CMD_DUL)); - lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0); + FLAG(cmd, PCI_HT_PRI_CMD_DD)); if (rid >= 0x22) - fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c > 8, - FLAG(lctr0, PCI_HT_LCTR_ISOCEN), - FLAG(lctr0, PCI_HT_LCTR_LSEN), - FLAG(lctr0, PCI_HT_LCTR_EXTCTL), - FLAG(lctr0, PCI_HT_LCTR_64B)); - lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0); + (lctr0 & PCI_HT_LCTR_CRCERR) >> 8); if (rid >= 0x22) - fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n"; + printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c", + FLAG(lctr0, PCI_HT_LCTR_ISOCEN), + FLAG(lctr0, PCI_HT_LCTR_LSEN), + FLAG(lctr0, PCI_HT_LCTR_EXTCTL), + FLAG(lctr0, PCI_HT_LCTR_64B)); + printf("\n"); + + lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0); + if (rid < 0x22) + printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n", + ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI), + ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4), + ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8), + ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12)); else - fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n"; - printf(fmt, - ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI), - ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4), - ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8), - ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12), - FLAG(lcnf0, PCI_HT_LCNF_DFI), - FLAG(lcnf0, PCI_HT_LCNF_DFO), - FLAG(lcnf0, PCI_HT_LCNF_DFIE), - FLAG(lcnf0, PCI_HT_LCNF_DFOE)); + printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n", + ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI), + FLAG(lcnf0, PCI_HT_LCNF_DFI), + ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4), + FLAG(lcnf0, PCI_HT_LCNF_DFO), + ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8), + FLAG(lcnf0, PCI_HT_LCNF_DFIE), + ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12), + FLAG(lcnf0, PCI_HT_LCNF_DFOE)); + lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1); - if (rid >= 0x22) - fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c > 8, + (lctr1 & PCI_HT_LCTR_CRCERR) >> 8); + if (rid >= 0x22) + printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c", FLAG(lctr1, PCI_HT_LCTR_ISOCEN), FLAG(lctr1, PCI_HT_LCTR_LSEN), FLAG(lctr1, PCI_HT_LCTR_EXTCTL), FLAG(lctr1, PCI_HT_LCTR_64B)); + printf("\n"); + lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1); - if (rid >= 0x22) - fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n"; + if (rid < 0x22) + printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n", + ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI), + ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4), + ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8), + ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12)); else - fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n"; - printf(fmt, - ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI), - ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4), - ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8), - ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12), - FLAG(lcnf1, PCI_HT_LCNF_DFI), - FLAG(lcnf1, PCI_HT_LCNF_DFO), - FLAG(lcnf1, PCI_HT_LCNF_DFIE), - FLAG(lcnf1, PCI_HT_LCNF_DFOE)); + printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n", + ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI), + FLAG(lcnf1, PCI_HT_LCNF_DFI), + ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4), + FLAG(lcnf1, PCI_HT_LCNF_DFO), + ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8), + FLAG(lcnf1, PCI_HT_LCNF_DFIE), + ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12), + FLAG(lcnf1, PCI_HT_LCNF_DFOE)); + printf("\t\tRevision ID: %u.%02u\n", (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN)); if (rid < 0x22) return; + lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0); printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ)); printf("\t\tLink Error 0: > 12)); w = get_conf_word(d, where + PCI_EXP_DEVSTA); - printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n", + printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n", FLAG(w, PCI_EXP_DEVSTA_CED), FLAG(w, PCI_EXP_DEVSTA_NFED), FLAG(w, PCI_EXP_DEVSTA_FED), @@ -728,11 +749,22 @@ static char *link_speed(int speed) return "8GT/s"; case 4: return "16GT/s"; + case 5: + return "32GT/s"; default: return "unknown"; } } +static char *link_compare(int sta, int cap) +{ + if (sta < cap) + return "downgraded"; + if (sta > cap) + return "strange"; + return "ok"; +} + static char *aspm_support(int code) { switch (code) @@ -758,14 +790,16 @@ static const char *aspm_enabled(int code) static void cap_express_link(struct device *d, int where, int type) { - u32 t, aspm; + u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width; u16 w; t = get_conf_long(d, where + PCI_EXP_LNKCAP); aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10; + cap_speed = t & PCI_EXP_LNKCAP_SPEED; + cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4; printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s", t >> 24, - link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4, + link_speed(cap_speed), cap_width, aspm_support(aspm)); if (aspm) { @@ -788,7 +822,7 @@ static void cap_express_link(struct device *d, int where, int type) printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM)); if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE)) - printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64); + printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64); printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n", FLAG(w, PCI_EXP_LNKCTL_DISABLE), FLAG(w, PCI_EXP_LNKCTL_CLOCK), @@ -799,9 +833,14 @@ static void cap_express_link(struct device *d, int where, int type) FLAG(w, PCI_EXP_LNKCTL_AUTBWIE)); w = get_conf_word(d, where + PCI_EXP_LNKSTA); - printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n", - link_speed(w & PCI_EXP_LNKSTA_SPEED), - (w & PCI_EXP_LNKSTA_WIDTH) >> 4, + sta_speed = w & PCI_EXP_LNKSTA_SPEED; + sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4; + printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n", + link_speed(sta_speed), + link_compare(sta_speed, cap_speed), + sta_width, + link_compare(sta_width, cap_width)); + printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n", FLAG(w, PCI_EXP_LNKSTA_TR_ERR), FLAG(w, PCI_EXP_LNKSTA_TRAIN), FLAG(w, PCI_EXP_LNKSTA_SL_CLK), @@ -867,7 +906,13 @@ static void cap_express_slot(struct device *d, int where) static void cap_express_root(struct device *d, int where) { - u32 w = get_conf_word(d, where + PCI_EXP_RTCTL); + u32 w; + + w = get_conf_word(d, where + PCI_EXP_RTCAP); + printf("\t\tRootCap: CRSVisible%c\n", + FLAG(w, PCI_EXP_RTCAP_CRSVIS)); + + w = get_conf_word(d, where + PCI_EXP_RTCTL); printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n", FLAG(w, PCI_EXP_RTCTL_SECEE), FLAG(w, PCI_EXP_RTCTL_SENFEE), @@ -875,10 +920,6 @@ static void cap_express_root(struct device *d, int where) FLAG(w, PCI_EXP_RTCTL_PMEIE), FLAG(w, PCI_EXP_RTCTL_CRSVIS)); - w = get_conf_word(d, where + PCI_EXP_RTCAP); - printf("\t\tRootCap: CRSVisible%c\n", - FLAG(w, PCI_EXP_RTCAP_CRSVIS)); - w = get_conf_long(d, where + PCI_EXP_RTSTA); printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n", w & PCI_EXP_RTSTA_PME_REQID, @@ -955,6 +996,52 @@ static const char *cap_express_devcap2_obff(int obff) } } +static const char *cap_express_devcap2_epr(int epr) +{ + switch (epr) + { + case 1: + return "Dev Specific"; + case 2: + return "Form Factor Dev Specific"; + case 3: + return "Reserved"; + default: + return "Not Supported"; + } +} + +static const char *cap_express_devcap2_lncls(int lncls) +{ + switch (lncls) + { + case 1: + return "64byte cachelines"; + case 2: + return "128byte cachelines"; + case 3: + return "Reserved"; + default: + return "Not Supported"; + } +} + +static const char *cap_express_devcap2_tphcomp(int tph) +{ + switch (tph) + { + case 1: + return "TPHComp+ ExtTPHComp-"; + case 2: + /* Reserved; intentionally left blank */ + return ""; + case 3: + return "TPHComp+ ExtTPHComp+"; + default: + return "TPHComp- ExtTPHComp-"; + } +} + static const char *cap_express_devctl2_obff(int obff) { switch (obff) @@ -997,11 +1084,36 @@ static void cap_express_dev2(struct device *d, int where, int type) int has_mem_bar = device_has_memory_space_bar(d); l = get_conf_long(d, where + PCI_EXP_DEVCAP2); - printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s", - cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)), - FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS), - FLAG(l, PCI_EXP_DEVCAP2_LTR), - cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l))); + printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c", + cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)), + FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS), + FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP), + FLAG(l, PCI_EXP_DEVCAP2_LTR)); + printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c", + FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP), + FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ), + cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)), + FLAG(l, PCI_EXP_DEVCAP2_EXTFMT), + FLAG(l, PCI_EXP_DEVCAP2_EE_TLP)); + + if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP)) + { + printf(", MaxEETLPPrefixes %d", + PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4); + } + + printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c", + cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)), + FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT)); + printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS)); + + if (type == PCI_EXP_TYPE_ROOT_PORT) + printf(" LN System CLS %s,", + cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l))); + + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT) + printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l))); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM) printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI)); else @@ -1022,7 +1134,7 @@ static void cap_express_dev2(struct device *d, int where, int type) } w = get_conf_word(d, where + PCI_EXP_DEVCTL2); - printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s", + printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c OBFF %s,", cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)), FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS), FLAG(w, PCI_EXP_DEV2_LTR), @@ -1046,6 +1158,29 @@ static void cap_express_dev2(struct device *d, int where, int type) } } +static const char *cap_express_link2_speed_cap(int vector) +{ + /* + * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not + * permitted to skip support for any data rates between 2.5GT/s and the + * highest supported rate. + */ + if (vector & 0x60) + return "RsvdP"; + if (vector & 0x10) + return "2.5-32GT/s"; + if (vector & 0x08) + return "2.5-16GT/s"; + if (vector & 0x04) + return "2.5-8GT/s"; + if (vector & 0x02) + return "2.5-5GT/s"; + if (vector & 0x01) + return "2.5GT/s"; + + return "Unknown"; +} + static const char *cap_express_link2_speed(int type) { switch (type) @@ -1059,6 +1194,8 @@ static const char *cap_express_link2_speed(int type) return "8GT/s"; case 4: return "16GT/s"; + case 5: + return "32GT/s"; default: return "Unknown"; } @@ -1095,12 +1232,59 @@ static const char *cap_express_link2_transmargin(int type) } } +static const char *cap_express_link2_crosslink_res(int crosslink) +{ + switch (crosslink) + { + case 0: + return "unsupported"; + case 1: + return "Upstream Port"; + case 2: + return "Downstream Port"; + default: + return "incomplete"; + } +} + +static const char *cap_express_link2_component(int presence) +{ + switch (presence) + { + case 0: + return "Link Down - Not Determined"; + case 1: + return "Link Down - Not Present"; + case 2: + return "Link Down - Present"; + case 4: + return "Link Up - Present"; + case 5: + return "Link Up - Present and DRS Received"; + default: + return "Reserved"; + } +} + static void cap_express_link2(struct device *d, int where, int type) { + u32 l = 0; u16 w; if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) && (d->dev->dev != 0 || d->dev->func != 0))) { + /* Link Capabilities 2 was reserved before PCIe r3.0 */ + l = get_conf_long(d, where + PCI_EXP_LNKCAP2); + if (l) { + printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c " + "Retimer%c 2Retimers%c DRS%c\n", + cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)), + FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK), + FLAG(l, PCI_EXP_LNKCAP2_RETIMER), + FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS), + FLAG(l, PCI_EXP_LNKCAP2_DRS)); + } + w = get_conf_word(d, where + PCI_EXP_LNKCTL2); printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c", cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)), @@ -1119,14 +1303,26 @@ static void cap_express_link2(struct device *d, int where, int type) } w = get_conf_word(d, where + PCI_EXP_LNKSTA2); - printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c, EqualizationPhase1%c\n" - "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n", + printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n" + "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n" + "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s", cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)), FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP), FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1), FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2), FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3), - FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ)); + FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ), + FLAG(w, PCI_EXP_LINKSTA2_RETIMER), + FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS), + cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w))); + + if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) { + printf(", DRS%c\n" + "\t\t\t DownstreamComp: %s\n", + FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD), + cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w))); + } else + printf("\n"); } static void cap_express_slot2(struct device *d UNUSED, int where UNUSED) @@ -1190,7 +1386,7 @@ cap_express(struct device *d, int where, int cap) size = 16; if (slot) size = 24; - if (type == PCI_EXP_TYPE_ROOT_PORT) + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) size = 32; if (!config_fetch(d, where + PCI_EXP_DEVCAP, size)) return type; @@ -1200,7 +1396,7 @@ cap_express(struct device *d, int where, int cap) cap_express_link(d, where, type); if (slot) cap_express_slot(d, where); - if (type == PCI_EXP_TYPE_ROOT_PORT) + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) cap_express_root(d, where); if ((cap & PCI_EXP_FLAGS_VERS) < 2) @@ -1506,6 +1702,9 @@ show_caps(struct device *d, int where) } switch (id) { + case PCI_CAP_ID_NULL: + printf("Null\n"); + break; case PCI_CAP_ID_PM: cap_pm(d, where, cap); break; @@ -1569,7 +1768,7 @@ show_caps(struct device *d, int where) cap_ea(d, where, cap); break; default: - printf("#%02x [%04x]\n", id, cap); + printf("Capability ID %#02x [%04x]\n", id, cap); } where = next; }