X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=lib%2Fi386-ports.c;h=5f8aea437a1f2d0ff7849f6dafd26839f1e0191b;hb=e5d1d2dbb64cafd33f9b012b7959b61319dcd250;hp=2e64fe4826238d358cc7aaca682a65b3797832d7;hpb=83d1cbf1e8bd451008271e2761f6f5826678241b;p=pciutils.git

diff --git a/lib/i386-ports.c b/lib/i386-ports.c
index 2e64fe4..5f8aea4 100644
--- a/lib/i386-ports.c
+++ b/lib/i386-ports.c
@@ -3,7 +3,9 @@
  *
  *	Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
  *
- *	Can be freely distributed and used under the terms of the GNU GPL.
+ *	Can be freely distributed and used under the terms of the GNU GPL v2+.
+ *
+ *	SPDX-License-Identifier: GPL-2.0-or-later
  */
 
 #define _GNU_SOURCE
@@ -28,6 +30,8 @@
 #include "i386-io-beos.h"
 #elif defined(PCI_OS_DJGPP)
 #include "i386-io-djgpp.h"
+#elif defined(PCI_OS_OPENBSD)
+#include "i386-io-openbsd.h"
 #else
 #error Do not know how to access I/O ports on this OS.
 #endif
@@ -114,12 +118,12 @@ conf1_detect(struct pci_access *a)
     }
 
   intel_io_lock();
-  outb (0x01, 0xCFB);
-  tmp = inl (0xCF8);
-  outl (0x80000000, 0xCF8);
-  if (inl (0xCF8) == 0x80000000)
+  intel_outb (0x01, 0xCFB);
+  tmp = intel_inl (0xCF8);
+  intel_outl (0x80000000, 0xCF8);
+  if (intel_inl (0xCF8) == 0x80000000)
     res = 1;
-  outl (tmp, 0xCF8);
+  intel_outl (tmp, 0xCF8);
   intel_io_unlock();
 
   if (res)
@@ -136,22 +140,23 @@ conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
   if (d->domain || pos >= 256)
     return 0;
 
+  if (len != 1 && len != 2 && len != 4)
+    return pci_generic_block_read(d, pos, buf, len);
+
   intel_io_lock();
-  outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
+  intel_outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 
   switch (len)
     {
     case 1:
-      buf[0] = inb(addr);
+      buf[0] = intel_inb(addr);
       break;
     case 2:
-      ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
+      ((u16 *) buf)[0] = cpu_to_le16(intel_inw(addr));
       break;
     case 4:
-      ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
+      ((u32 *) buf)[0] = cpu_to_le32(intel_inl(addr));
       break;
-    default:
-      res = pci_generic_block_read(d, pos, buf, len);
     }
 
   intel_io_unlock();
@@ -167,22 +172,23 @@ conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
   if (d->domain || pos >= 256)
     return 0;
 
+  if (len != 1 && len != 2 && len != 4)
+    return pci_generic_block_write(d, pos, buf, len);
+
   intel_io_lock();
-  outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
+  intel_outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 
   switch (len)
     {
     case 1:
-      outb(buf[0], addr);
+      intel_outb(buf[0], addr);
       break;
     case 2:
-      outw(le16_to_cpu(((u16 *) buf)[0]), addr);
+      intel_outw(le16_to_cpu(((u16 *) buf)[0]), addr);
       break;
     case 4:
-      outl(le32_to_cpu(((u32 *) buf)[0]), addr);
+      intel_outl(le32_to_cpu(((u32 *) buf)[0]), addr);
       break;
-    default:
-      res = pci_generic_block_write(d, pos, buf, len);
     }
   intel_io_unlock();
   return res;
@@ -206,10 +212,10 @@ conf2_detect(struct pci_access *a)
   /* This is ugly and tends to produce false positives. Beware. */
 
   intel_io_lock();
-  outb(0x00, 0xCFB);
-  outb(0x00, 0xCF8);
-  outb(0x00, 0xCFA);
-  if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
+  intel_outb(0x00, 0xCFB);
+  intel_outb(0x00, 0xCF8);
+  intel_outb(0x00, 0xCFA);
+  if (intel_inb(0xCF8) == 0x00 && intel_inb(0xCFA) == 0x00)
     res = intel_sanity_check(a, &pm_intel_conf2);
   intel_io_unlock();
   return res;
@@ -228,24 +234,25 @@ conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
     /* conf2 supports only 16 devices per bus */
     return 0;
 
+  if (len != 1 && len != 2 && len != 4)
+    return pci_generic_block_read(d, pos, buf, len);
+
   intel_io_lock();
-  outb((d->func << 1) | 0xf0, 0xcf8);
-  outb(d->bus, 0xcfa);
+  intel_outb((d->func << 1) | 0xf0, 0xcf8);
+  intel_outb(d->bus, 0xcfa);
   switch (len)
     {
     case 1:
-      buf[0] = inb(addr);
+      buf[0] = intel_inb(addr);
       break;
     case 2:
-      ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
+      ((u16 *) buf)[0] = cpu_to_le16(intel_inw(addr));
       break;
     case 4:
-      ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
+      ((u32 *) buf)[0] = cpu_to_le32(intel_inl(addr));
       break;
-    default:
-      res = pci_generic_block_read(d, pos, buf, len);
     }
-  outb(0, 0xcf8);
+  intel_outb(0, 0xcf8);
   intel_io_unlock();
   return res;
 }
@@ -263,25 +270,26 @@ conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
     /* conf2 supports only 16 devices per bus */
     return 0;
 
+  if (len != 1 && len != 2 && len != 4)
+    return pci_generic_block_write(d, pos, buf, len);
+
   intel_io_lock();
-  outb((d->func << 1) | 0xf0, 0xcf8);
-  outb(d->bus, 0xcfa);
+  intel_outb((d->func << 1) | 0xf0, 0xcf8);
+  intel_outb(d->bus, 0xcfa);
   switch (len)
     {
     case 1:
-      outb(buf[0], addr);
+      intel_outb(buf[0], addr);
       break;
     case 2:
-      outw(le16_to_cpu(* (u16 *) buf), addr);
+      intel_outw(le16_to_cpu(* (u16 *) buf), addr);
       break;
     case 4:
-      outl(le32_to_cpu(* (u32 *) buf), addr);
+      intel_outl(le32_to_cpu(* (u32 *) buf), addr);
       break;
-    default:
-      res = pci_generic_block_write(d, pos, buf, len);
     }
 
-  outb(0, 0xcf8);
+  intel_outb(0, 0xcf8);
   intel_io_unlock();
   return res;
 }