X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=lib%2Fi386-ports.c;h=2e64fe4826238d358cc7aaca682a65b3797832d7;hb=4582426202ad6ac6539305dae2c0b70016f014f4;hp=d491ad68320677c99f48dd42c1e73caafe072e4e;hpb=9007a292f24685d7c1ab51506fae8df22ced007f;p=pciutils.git

diff --git a/lib/i386-ports.c b/lib/i386-ports.c
index d491ad6..2e64fe4 100644
--- a/lib/i386-ports.c
+++ b/lib/i386-ports.c
@@ -10,7 +10,7 @@
 
 #include "internal.h"
 
-#include <unistd.h>
+#include <string.h>
 
 #if defined(PCI_OS_LINUX)
 #include "i386-io-linux.h"
@@ -20,6 +20,14 @@
 #include "i386-io-sunos.h"
 #elif defined(PCI_OS_WINDOWS)
 #include "i386-io-windows.h"
+#elif defined(PCI_OS_CYGWIN)
+#include "i386-io-cygwin.h"
+#elif defined(PCI_OS_HAIKU)
+#include "i386-io-haiku.h"
+#elif defined(PCI_OS_BEOS)
+#include "i386-io-beos.h"
+#elif defined(PCI_OS_DJGPP)
+#include "i386-io-djgpp.h"
 #else
 #error Do not know how to access I/O ports on this OS.
 #endif
@@ -27,25 +35,28 @@
 static int conf12_io_enabled = -1;		/* -1=haven't tried, 0=failed, 1=succeeded */
 
 static int
-conf12_setup_io(void)
+conf12_setup_io(struct pci_access *a)
 {
   if (conf12_io_enabled < 0)
-    conf12_io_enabled = intel_setup_io();
+    conf12_io_enabled = intel_setup_io(a);
   return conf12_io_enabled;
 }
 
 static void
 conf12_init(struct pci_access *a)
 {
-  if (!conf12_setup_io())
+  if (!conf12_setup_io(a))
     a->error("No permission to access I/O ports (you probably have to be root).");
 }
 
 static void
-conf12_cleanup(struct pci_access *a UNUSED)
+conf12_cleanup(struct pci_access *a)
 {
   if (conf12_io_enabled > 0)
-    conf12_io_enabled = intel_cleanup_io();
+    {
+      intel_cleanup_io(a);
+      conf12_io_enabled = -1;
+    }
 }
 
 /*
@@ -64,10 +75,11 @@ intel_sanity_check(struct pci_access *a, struct pci_methods *m)
 {
   struct pci_dev d;
 
+  memset(&d, 0, sizeof(d));
   a->debug("...sanity check");
   d.bus = 0;
   d.func = 0;
-  for(d.dev = 0; d.dev < 32; d.dev++)
+  for (d.dev = 0; d.dev < 32; d.dev++)
     {
       u16 class, vendor;
       if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
@@ -95,17 +107,21 @@ conf1_detect(struct pci_access *a)
   unsigned int tmp;
   int res = 0;
 
-  if (!conf12_setup_io())
+  if (!conf12_setup_io(a))
     {
       a->debug("...no I/O permission");
       return 0;
     }
+
+  intel_io_lock();
   outb (0x01, 0xCFB);
   tmp = inl (0xCF8);
   outl (0x80000000, 0xCF8);
   if (inl (0xCF8) == 0x80000000)
     res = 1;
   outl (tmp, 0xCF8);
+  intel_io_unlock();
+
   if (res)
     res = intel_sanity_check(a, &pm_intel_conf1);
   return res;
@@ -115,10 +131,12 @@ static int
 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
 {
   int addr = 0xcfc + (pos&3);
+  int res = 1;
 
-  if (pos >= 256)
+  if (d->domain || pos >= 256)
     return 0;
 
+  intel_io_lock();
   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 
   switch (len)
@@ -133,19 +151,23 @@ conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
       break;
     default:
-      return pci_generic_block_read(d, pos, buf, len);
+      res = pci_generic_block_read(d, pos, buf, len);
     }
-  return 1;
+
+  intel_io_unlock();
+  return res;
 }
 
 static int
 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
 {
   int addr = 0xcfc + (pos&3);
+  int res = 1;
 
-  if (pos >= 256)
+  if (d->domain || pos >= 256)
     return 0;
 
+  intel_io_lock();
   outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
 
   switch (len)
@@ -160,9 +182,10 @@ conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
       outl(le32_to_cpu(((u32 *) buf)[0]), addr);
       break;
     default:
-      return pci_generic_block_write(d, pos, buf, len);
+      res = pci_generic_block_write(d, pos, buf, len);
     }
-  return 1;
+  intel_io_unlock();
+  return res;
 }
 
 /*
@@ -172,7 +195,9 @@ conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
 static int
 conf2_detect(struct pci_access *a)
 {
-  if (!conf12_setup_io())
+  int res = 0;
+
+  if (!conf12_setup_io(a))
     {
       a->debug("...no I/O permission");
       return 0;
@@ -180,26 +205,30 @@ conf2_detect(struct pci_access *a)
 
   /* This is ugly and tends to produce false positives. Beware. */
 
+  intel_io_lock();
   outb(0x00, 0xCFB);
   outb(0x00, 0xCF8);
   outb(0x00, 0xCFA);
   if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
-    return intel_sanity_check(a, &pm_intel_conf2);
-  else
-    return 0;
+    res = intel_sanity_check(a, &pm_intel_conf2);
+  intel_io_unlock();
+  return res;
 }
 
 static int
 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
 {
+  int res = 1;
   int addr = 0xc000 | (d->dev << 8) | pos;
 
-  if (pos >= 256)
+  if (d->domain || pos >= 256)
     return 0;
 
   if (d->dev >= 16)
     /* conf2 supports only 16 devices per bus */
     return 0;
+
+  intel_io_lock();
   outb((d->func << 1) | 0xf0, 0xcf8);
   outb(d->bus, 0xcfa);
   switch (len)
@@ -214,23 +243,27 @@ conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
       ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
       break;
     default:
-      outb(0, 0xcf8);
-      return pci_generic_block_read(d, pos, buf, len);
+      res = pci_generic_block_read(d, pos, buf, len);
     }
   outb(0, 0xcf8);
-  return 1;
+  intel_io_unlock();
+  return res;
 }
 
 static int
 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
 {
+  int res = 1;
   int addr = 0xc000 | (d->dev << 8) | pos;
 
-  if (pos >= 256)
+  if (d->domain || pos >= 256)
     return 0;
 
   if (d->dev >= 16)
-    d->access->error("conf2_write: only first 16 devices exist.");
+    /* conf2 supports only 16 devices per bus */
+    return 0;
+
+  intel_io_lock();
   outb((d->func << 1) | 0xf0, 0xcf8);
   outb(d->bus, 0xcfa);
   switch (len)
@@ -245,15 +278,17 @@ conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
       outl(le32_to_cpu(* (u32 *) buf), addr);
       break;
     default:
-      outb(0, 0xcf8);
-      return pci_generic_block_write(d, pos, buf, len);
+      res = pci_generic_block_write(d, pos, buf, len);
     }
+
   outb(0, 0xcf8);
-  return 1;
+  intel_io_unlock();
+  return res;
 }
 
 struct pci_methods pm_intel_conf1 = {
-  "Intel-conf1",
+  "intel-conf1",
+  "Raw I/O port access using Intel conf1 interface",
   NULL,					/* config */
   conf1_detect,
   conf12_init,
@@ -262,12 +297,14 @@ struct pci_methods pm_intel_conf1 = {
   pci_generic_fill_info,
   conf1_read,
   conf1_write,
+  NULL,					/* read_vpd */
   NULL,					/* init_dev */
   NULL					/* cleanup_dev */
 };
 
 struct pci_methods pm_intel_conf2 = {
-  "Intel-conf2",
+  "intel-conf2",
+  "Raw I/O port access using Intel conf2 interface",
   NULL,					/* config */
   conf2_detect,
   conf12_init,
@@ -276,6 +313,7 @@ struct pci_methods pm_intel_conf2 = {
   pci_generic_fill_info,
   conf2_read,
   conf2_write,
+  NULL,					/* read_vpd */
   NULL,					/* init_dev */
   NULL					/* cleanup_dev */
 };