X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=lib%2Fheader.h;h=e74f6d80e8c00c22b1636e50f7fd76aceb6bb8dd;hb=e16f124617c9133f63076ad23653fe548d031e44;hp=bfdcc80fbae0f31701fc719e30a446d6585d0469;hpb=33226851677b92fffd186002d74a1a515fb49413;p=pciutils.git diff --git a/lib/header.h b/lib/header.h index bfdcc80..e74f6d8 100644 --- a/lib/header.h +++ b/lib/header.h @@ -219,7 +219,7 @@ #define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */ #define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */ #define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */ -#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */ +#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */ #define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */ #define PCI_EXT_CAP_ID_RCRB 0x0a /* Root Complex Register Block */ @@ -252,6 +252,7 @@ #define PCI_EXT_CAP_ID_LMR 0x27 /* Lane Margining at Receiver */ #define PCI_EXT_CAP_ID_HIER_ID 0x28 /* Hierarchy ID */ #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ +#define PCI_EXT_CAP_ID_DOE 0x2e /* Data Object Exchange */ /*** Definitions of capabilities ***/ @@ -536,7 +537,7 @@ #define PCI_HT_SEC_CMD 2 /* Command Register */ #define PCI_HT_SEC_CMD_WR 0x0001 /* Warm Reset */ #define PCI_HT_SEC_CMD_DE 0x0002 /* Double-Ended */ -#define PCI_HT_SEC_CMD_DN 0x0076 /* Device Number */ +#define PCI_HT_SEC_CMD_DN 0x007c /* Device Number */ #define PCI_HT_SEC_CMD_CS 0x0080 /* Chain Side */ #define PCI_HT_SEC_CMD_HH 0x0100 /* Host Hide */ #define PCI_HT_SEC_CMD_AS 0x0400 /* Act as Slave */ @@ -873,6 +874,13 @@ #define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */ #define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */ #define PCI_EXP_DEVCAP2 0x24 /* Device capabilities 2 */ +#define PCI_EXP_DEVCAP2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */ +#define PCI_EXP_DEVCAP2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */ +#define PCI_EXP_DEVCAP2_ARI 0x0020 /* ARI Forwarding Supported */ +#define PCI_EXP_DEVCAP2_ATOMICOP_ROUTING 0x0040 /* AtomicOp Routing Supported */ +#define PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP 0x0080 /* 32bit AtomicOp Completer Supported */ +#define PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP 0x0100 /* 64bit AtomicOp Completer Supported */ +#define PCI_EXP_DEVCAP2_128BIT_CAS_COMP 0x0200 /* 128bit CAS Completer Supported */ #define PCI_EXP_DEVCAP2_NROPRPRP 0x0400 /* No RO-enabled PR-PR Passing */ #define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */ #define PCI_EXP_DEVCAP2_TPH_COMP(x) (((x) >> 12) & 3) /* TPH Completer Supported */ @@ -887,20 +895,21 @@ #define PCI_EXP_DEVCAP2_EPR_INIT 0x04000000 /* Emergency Power Reduction Initialization Required */ #define PCI_EXP_DEVCAP2_FRS 0x80000000 /* FRS supported */ #define PCI_EXP_DEVCTL2 0x28 /* Device Control */ -#define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */ -#define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */ -#define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */ -#define PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */ -#define PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */ -#define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */ -#define PCI_EXP_DEVCAP2_ATOMICOP_ROUTING 0x0040 /* AtomicOp Routing Supported */ -#define PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP 0x0080 /* 32bit AtomicOp Completer Supported */ -#define PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP 0x0100 /* 64bit AtomicOp Completer Supported */ -#define PCI_EXP_DEVCAP2_128BIT_CAS_COMP 0x0200 /* 128bit CAS Completer Supported */ -#define PCI_EXP_DEV2_LTR 0x0400 /* LTR enabled */ -#define PCI_EXP_DEV2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */ +#define PCI_EXP_DEVCTL2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */ +#define PCI_EXP_DEVCTL2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable */ +#define PCI_EXP_DEVCTL2_ARI 0x0020 /* ARI Forwarding */ +#define PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */ +#define PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */ +#define PCI_EXP_DEVCTL2_LTR 0x0400 /* LTR enabled */ +#define PCI_EXP_DEVCTL2_10BIT_TAG_REQ 0x1000 /* 10 Bit Tag Requester enabled */ +#define PCI_EXP_DEVCTL2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */ #define PCI_EXP_DEVSTA2 0x2a /* Device Status */ #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */ +#define PCI_EXP_LNKCAP2_SPEED(x) (((x) >> 1) & 0x7f) +#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink Supported */ +#define PCI_EXP_LNKCAP2_RETIMER 0x00800000 /* Retimer Supported */ +#define PCI_EXP_LNKCAP2_2RETIMERS 0x01000000 /* 2 Retimers Supported */ +#define PCI_EXP_LNKCAP2_DRS 0x80000000 /* Device Readiness Status */ #define PCI_EXP_LNKCTL2 0x30 /* Link Control */ #define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */ #define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */ @@ -909,7 +918,7 @@ #define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */ #define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance */ #define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */ -#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 0xf) /* Compliance De-emphasis */ +#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 0xf) /* Compliance Preset/De-emphasis */ #define PCI_EXP_LNKSTA2 0x32 /* Link Status */ #define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current De-emphasis Level */ #define PCI_EXP_LINKSTA2_EQU_COMP 0x02 /* Equalization Complete */ @@ -917,6 +926,11 @@ #define PCI_EXP_LINKSTA2_EQU_PHASE2 0x08 /* Equalization Phase 2 Successful */ #define PCI_EXP_LINKSTA2_EQU_PHASE3 0x10 /* Equalization Phase 3 Successful */ #define PCI_EXP_LINKSTA2_EQU_REQ 0x20 /* Link Equalization Request */ +#define PCI_EXP_LINKSTA2_RETIMER 0x0040 /* Retimer Detected */ +#define PCI_EXP_LINKSTA2_2RETIMERS 0x0080 /* 2 Retimers Detected */ +#define PCI_EXP_LINKSTA2_CROSSLINK(x) (((x) >> 8) & 0x3) /* Crosslink Res */ +#define PCI_EXP_LINKSTA2_COMPONENT(x) (((x) >> 12) & 0x7) /* Presence */ +#define PCI_EXP_LINKSTA2_DRS_RCVD 0x8000 /* DRS Msg Received */ #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */ #define PCI_EXP_SLTCTL2 0x38 /* Slot Control */ #define PCI_EXP_SLTSTA2 0x3a /* Slot Status */ @@ -1038,10 +1052,83 @@ #define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64-bit) */ #define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */ +/* Root Complex Event Collector Endpoint Association */ +#define PCI_RCEC_EP_CAP_VER(reg) (((reg) >> 16) & 0xf) +#define PCI_RCEC_BUSN_REG_VER 0x02 /* as per PCIe sec 7.9.10.1 */ +#define PCI_RCEC_RCIEP_BMAP 0x0004 /* as per PCIe sec 7.9.10.2 */ +#define PCI_RCEC_BUSN_REG 0x0008 /* as per PCIe sec 7.9.10.3 */ + /* PCIe Vendor-Specific Capability */ #define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */ #define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */ +/* PCIe Designated Vendor-Specific Capability */ +#define PCI_DVSEC_HEADER1 4 /* Designated Vendor-Specific Header 1 */ +#define PCI_DVSEC_HEADER2 8 /* Designated Vendor-Specific Header 2 */ +#define PCI_DVSEC_VENDOR_ID_CXL 0x1e98 /* Designated Vendor-Specific Vendor ID for CXL */ +#define PCI_DVSEC_ID_CXL 0 /* Designated Vendor-Specific ID for Intel CXL */ + +/* PCIe CXL Designated Vendor-Specific Capabilities for Devices: Control, Status */ +#define PCI_CXL_DEV_LEN 0x38 /* CXL Device DVSEC Length */ +#define PCI_CXL_DEV_CAP 0x0a /* CXL Capability Register */ +#define PCI_CXL_DEV_CAP_CACHE 0x0001 /* CXL.cache Protocol Support */ +#define PCI_CXL_DEV_CAP_IO 0x0002 /* CXL.io Protocol Support */ +#define PCI_CXL_DEV_CAP_MEM 0x0004 /* CXL.mem Protocol Support */ +#define PCI_CXL_DEV_CAP_MEM_HWINIT 0x0008 /* CXL.mem Initializes with HW/FW Support */ +#define PCI_CXL_DEV_CAP_HDM_CNT(x) (((x) & (3 << 4)) >> 4) /* CXL Number of HDM ranges */ +#define PCI_CXL_DEV_CAP_VIRAL 0x4000 /* CXL Viral Handling Support */ +#define PCI_CXL_DEV_CTRL 0x0c /* CXL Control Register */ +#define PCI_CXL_DEV_CTRL_CACHE 0x0001 /* CXL.cache Protocol Enable */ +#define PCI_CXL_DEV_CTRL_IO 0x0002 /* CXL.io Protocol Enable */ +#define PCI_CXL_DEV_CTRL_MEM 0x0004 /* CXL.mem Protocol Enable */ +#define PCI_CXL_DEV_CTRL_CACHE_SF_COV(x) (((x) & (0x1f << 3)) >> 3) /* Snoop Filter Coverage */ +#define PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(x) (((x) & (0x7 << 8)) >> 8) /* Snoop Filter Granularity */ +#define PCI_CXL_DEV_CTRL_CACHE_CLN 0x0800 /* CXL.cache Performance Hint on Clean Evictions */ +#define PCI_CXL_DEV_CTRL_VIRAL 0x4000 /* CXL Viral Handling Enable */ +#define PCI_CXL_DEV_STATUS 0x0e /* CXL Status Register */ +#define PCI_CXL_DEV_STATUS_VIRAL 0x4000 /* CXL Viral Handling Status */ +#define PCI_CXL_DEV_STATUS2 0x12 +#define PCI_CXL_DEV_STATUS_CACHE_INV 0x0001 +#define PCI_CXL_DEV_STATUS_RC 0x0002 /* Device Reset Complete */ +#define PCI_CXL_DEV_STATUS_RE 0x0004 /* Device Reset Error */ +#define PCI_CXL_DEV_STATUS_PMC 0x8000 /* Power Management Init Complete */ +#define PCI_CXL_DEV_CAP2 0x16 +#define PCI_CXL_DEV_CAP2_CACHE_UNK 0x0000 /* Cache Size Isn't Reported */ +#define PCI_CXL_DEV_CAP2_CACHE_64K 0x0001 /* Unit Size 64K */ +#define PCI_CXL_DEV_CAP2_CACHE_1M 0x0002 /* Unit Size 1M */ +#define PCI_CXL_DEV_RANGE1_SIZE_HI 0x18 +#define PCI_CXL_DEV_RANGE1_SIZE_LO 0x1c +#define PCI_CXL_RANGE_VALID 0x0001 +#define PCI_CXL_RANGE_ACTIVE 0x0002 +#define PCI_CXL_RANGE_TYPE(x) (((x) >> 2) & 0x7) +#define PCI_CXL_RANGE_CLASS(x) (((x) >> 5) & 0x7) +#define PCI_CXL_RANGE_INTERLEAVE(x) (((x) >> 8) & 0x1f) +#define PCI_CXL_RANGE_TIMEOUT(x) (((x) >> 13) & 0x7) +#define PCI_CXL_DEV_RANGE1_BASE_HI 0x20 +#define PCI_CXL_DEV_RANGE1_BASE_LO 0x24 +#define PCI_CXL_DEV_RANGE2_SIZE_HI 0x28 +#define PCI_CXL_DEV_RANGE2_SIZE_LO 0x2c +#define PCI_CXL_DEV_RANGE2_BASE_HI 0x30 +#define PCI_CXL_DEV_RANGE2_BASE_LO 0x34 + +/* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Ports */ +#define PCI_CXL_PORT_EXT_LEN 0x28 /* CXL Extensions DVSEC for Ports Length */ +#define PCI_CXL_PORT_EXT_STATUS 0x0a /* Port Extension Status */ +#define PCI_CXL_PORT_PM_INIT_COMPLETE 0x1 /* Port Power Management Initialization Complete */ +#define PCI_CXL_PORT_CTRL 0x0c /* Port Control Override */ +#define PCI_CXL_PORT_UNMASK_SBR 0x0001 /* Unmask SBR */ +#define PCI_CXL_PORT_UNMASK_LINK 0x0002 /* Unmask Link Disable */ +#define PCI_CXL_PORT_ALT_MEMORY 0x0004 /* Alt Memory and ID Space Enable */ +#define PCI_CXL_PORT_ALT_BME 0x0008 /* Alt BME */ +#define PCI_CXL_PORT_VIRAL_EN 0x4000 /* Viral Enable */ +#define PCI_CXL_PORT_ALT_BUS_BASE 0xe +#define PCI_CXL_PORT_ALT_BUS_LIMIT 0xf +#define PCI_CXL_PORT_ALT_MEM_BASE 0x10 +#define PCI_CXL_PORT_ALT_MEM_LIMIT 0x12 + +/* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Register Locator */ +#define PCI_CXL_RL_BLOCK1_LO 0x0c + /* Access Control Services */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ #define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */ @@ -1082,6 +1169,7 @@ /* Single Root I/O Virtualization */ #define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */ #define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */ +#define PCI_IOV_CAP_VF_10BIT_TAG_REQ 0x00000004 /* VF 10-Bit Tag Requester Supported */ #define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Message Number */ #define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */ #define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */ @@ -1089,6 +1177,7 @@ #define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */ #define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */ #define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */ +#define PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN 0x0020 /* VF 10-Bit Tag Requester Enable */ #define PCI_IOV_STATUS 0x0a /* SR-IOV Status Register */ #define PCI_IOV_STATUS_MS 0x0001 /* VF Migration Status */ #define PCI_IOV_INITIALVF 0x0c /* Number of VFs that are initially associated */ @@ -1173,7 +1262,7 @@ #define PCI_DPC_CAP 4 /* DPC Capability */ #define PCI_DPC_CAP_INT_MSG(x) ((x) & 0x1f) /* DPC Interrupt Message Number */ -#define PCI_DPC_CAP_RP_EXT 0x20 /* DPC Root Port Extentions */ +#define PCI_DPC_CAP_RP_EXT 0x20 /* DPC Root Port Extensions */ #define PCI_DPC_CAP_TLP_BLOCK 0x40 /* DPC Poisoned TLP Egress Blocking */ #define PCI_DPC_CAP_SW_TRIGGER 0x80 /* DPC Software Trigger */ #define PCI_DPC_CAP_RP_LOG(x) (((x) >> 8) & 0xf) /* DPC RP PIO Log Size */ @@ -1191,7 +1280,7 @@ #define PCI_DPC_STS_REASON(x) (((x) >> 1) & 0x3) /* DPC Trigger Reason */ #define PCI_DPC_STS_INT 0x08 /* DPC Interrupt Status */ #define PCI_DPC_STS_RP_BUSY 0x10 /* DPC Root Port Busy */ -#define PCI_DPC_STS_TRIGGER_EXT(x) (((x) >> 5) & 0x3) /* Trigger Reason Extention */ +#define PCI_DPC_STS_TRIGGER_EXT(x) (((x) >> 5) & 0x3) /* Trigger Reason Extension */ #define PCI_DPC_STS_PIO_FEP(x) (((x) >> 8) & 0x1f) /* DPC PIO First Error Pointer */ #define PCI_DPC_SOURCE 10 /* DPC Source ID */ @@ -1201,7 +1290,7 @@ #define PCI_L1PM_SUBSTAT_CAP_PM_L11 0x2 /* PCI-PM L1.1 Supported */ #define PCI_L1PM_SUBSTAT_CAP_ASPM_L12 0x4 /* ASPM L1.2 Supported */ #define PCI_L1PM_SUBSTAT_CAP_ASPM_L11 0x8 /* ASPM L1.1 Supported */ -#define PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP 0x16 /* L1 PM Substates supported */ +#define PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP 0x10 /* L1 PM Substates supported */ #define PCI_L1PM_SUBSTAT_CTL1 0x8 /* L1 PM Substate Control 1 */ #define PCI_L1PM_SUBSTAT_CTL1_PM_L12 0x1 /* PCI-PM L1.2 Enable */ #define PCI_L1PM_SUBSTAT_CTL1_PM_L11 0x2 /* PCI-PM L1.1 Enable */ @@ -1209,6 +1298,20 @@ #define PCI_L1PM_SUBSTAT_CTL1_ASPM_L11 0x8 /* ASPM L1.1 Enable */ #define PCI_L1PM_SUBSTAT_CTL2 0xC /* L1 PM Substate Control 2 */ +/* Data Object Exchange Extended Capability */ +#define PCI_DOE_CAP 0x4 /* DOE Capabilities Register */ +#define PCI_DOE_CAP_INT_SUPP 0x1 /* Interrupt Support */ +#define PCI_DOE_CAP_INT_MSG(x) (((x) >> 1) & 0x7ff) /* DOE Interrupt Message Number */ +#define PCI_DOE_CTL 0x8 /* DOE Control Register */ +#define PCI_DOE_CTL_ABORT 0x1 /* DOE Abort */ +#define PCI_DOE_CTL_INT 0x2 /* DOE Interrupt Enable */ +#define PCI_DOE_CTL_GO 0x80000000 /* DOE Go */ +#define PCI_DOE_STS 0xC /* DOE Status Register */ +#define PCI_DOE_STS_BUSY 0x1 /* DOE Busy */ +#define PCI_DOE_STS_INT 0x2 /* DOE Interrupt Status */ +#define PCI_DOE_STS_ERROR 0x3 /* DOE Error */ +#define PCI_DOE_STS_OBJECT_READY 0x80000000 /* Data Object Ready */ + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded @@ -1357,4 +1460,10 @@ /* I/O resource flags, compatible with */ +#define PCI_IORESOURCE_TYPE_BITS 0x00001f00 +#define PCI_IORESOURCE_IO 0x00000100 +#define PCI_IORESOURCE_MEM 0x00000200 +#define PCI_IORESOURCE_PREFETCH 0x00002000 +#define PCI_IORESOURCE_MEM_64 0x00100000 +#define PCI_IORESOURCE_IO_16BIT_ADDR (1<<0) #define PCI_IORESOURCE_PCI_EA_BEI (1<<5)