X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=lib%2Fheader.h;h=cc69a5189be93e707d970a9462bcc3de3a130a35;hb=9e567a4e5a8ca4bdd097ff6707fc6a517ca8d177;hp=33ed2be7866690cde4f4ec5e6c321e4f75aa205f;hpb=8683ca3b20878a24ae1166111a635ee1c0c7b16e;p=pciutils.git diff --git a/lib/header.h b/lib/header.h index 33ed2be..cc69a51 100644 --- a/lib/header.h +++ b/lib/header.h @@ -537,7 +537,7 @@ #define PCI_HT_SEC_CMD 2 /* Command Register */ #define PCI_HT_SEC_CMD_WR 0x0001 /* Warm Reset */ #define PCI_HT_SEC_CMD_DE 0x0002 /* Double-Ended */ -#define PCI_HT_SEC_CMD_DN 0x0076 /* Device Number */ +#define PCI_HT_SEC_CMD_DN 0x007c /* Device Number */ #define PCI_HT_SEC_CMD_CS 0x0080 /* Chain Side */ #define PCI_HT_SEC_CMD_HH 0x0100 /* Host Hide */ #define PCI_HT_SEC_CMD_AS 0x0400 /* Act as Slave */ @@ -1127,12 +1127,60 @@ #define PCI_CXL_PORT_ALT_MEM_LIMIT 0x12 /* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Register Locator */ -#define PCI_CXL_RL_BASE0_LO 0x0c -#define PCI_CXL_RL_BASE0_HI 0x10 -#define PCI_CXL_RL_BASE1_LO 0x14 -#define PCI_CXL_RL_BASE1_HI 0x18 -#define PCI_CXL_RL_BASE2_LO 0x1c -#define PCI_CXL_RL_BASE2_HI 0x20 +#define PCI_CXL_RL_BLOCK1_LO 0x0c + +/* PCIe CXL Designated Vendor-Specific Capabilities for Global Persistent Flush */ +#define PCI_CXL_GPF_DEV_LEN 0x10 +#define PCI_CXL_GPF_DEV_PHASE2_DUR 0x0a /* GPF Phase 2 Duration Register */ +#define PCI_CXL_GPF_DEV_PHASE2_POW 0x0c /* GPF Phase 2 Power Register */ +#define PCI_CXL_GPF_DEV_1US 0x0 +#define PCI_CXL_GPF_DEV_10US 0x1 +#define PCI_CXL_GPF_DEV_100US 0x2 +#define PCI_CXL_GPF_DEV_1MS 0x3 +#define PCI_CXL_GPF_DEV_10MS 0x4 +#define PCI_CXL_GPF_DEV_100MS 0x5 +#define PCI_CXL_GPF_DEV_1S 0x6 +#define PCI_CXL_GPF_DEV_10S 0x7 + +/* PCIe CXL Designated Vendor-Specific Capabilities for Flex Bus Port */ +#define PCI_CXL_FB_LEN 0x20 +#define PCI_CXL_FB_PORT_CAP 0x0a /* CXL Flex Bus Port Capability Register */ +#define PCI_CXL_FB_CAP_CACHE 0x0001 /* CXL.cache Capable */ +#define PCI_CXL_FB_CAP_IO 0x0002 /* CXL.io Capable */ +#define PCI_CXL_FB_CAP_MEM 0x0004 /* CXL.mem Capable */ +#define PCI_CXL_FB_CAP_68B_FLIT 0x0020 /* CXL 68B Flit and VH Capable */ +#define PCI_CXL_FB_CAP_MULT_LOG_DEV 0x0040 /* CXL Multi-Logical Device Capable */ +#define PCI_CXL_FB_CAP_256B_FLIT 0x2000 /* CXL Latency Optimized 256B Flit Capable */ +#define PCI_CXL_FB_CAP_PBR_FLIT 0x4000 /* CXL PBR Flit Capable */ +#define PCI_CXL_FB_PORT_CTRL 0x0c /* CXL Flex Bus Port Control Register */ +#define PCI_CXL_FB_CTRL_CACHE 0x0001 /* CXL.cache Enable */ +#define PCI_CXL_FB_CTRL_IO 0x0002 /* CXL.io Enable */ +#define PCI_CXL_FB_CTRL_MEM 0x0004 /* CXL.mem Enable */ +#define PCI_CXL_FB_CTRL_SYNC_HDR_BYP 0x0008 /* CXL Sync Header Bypass Enable */ +#define PCI_CXL_FB_CTRL_DRFT_BUF 0x0010 /* Drift Buffer Enable */ +#define PCI_CXL_FB_CTRL_68B_FLIT 0x0020 /* CXL 68B Flit and VH Enable */ +#define PCI_CXL_FB_CTRL_MULT_LOG_DEV 0x0040 /* CXL Multi Logical Device Enable */ +#define PCI_CXL_FB_CTRL_RCD 0x0080 /* Disable RCD Training */ +#define PCI_CXL_FB_CTRL_RETIMER1 0x0100 /* Retimer1 Present */ +#define PCI_CXL_FB_CTRL_RETIMER2 0x0200 /* Retimer2 Present */ +#define PCI_CXL_FB_CTRL_256B_FLIT 0x2000 /* CXL Latency Optimized 256B Flit Enable */ +#define PCI_CXL_FB_CTRL_PBR_FLIT 0x4000 /* CXL PBR Flit Enable */ +#define PCI_CXL_FB_PORT_STATUS 0x0e /* CXL Flex Bus Port Status Register */ +#define PCI_CXL_FB_STAT_CACHE 0x0001 /* CXL.cache Enabled */ +#define PCI_CXL_FB_STAT_IO 0x0002 /* CXL.io Enabled */ +#define PCI_CXL_FB_STAT_MEM 0x0004 /* CXL.mem Enabled */ +#define PCI_CXL_FB_STAT_SYNC_HDR_BYP 0x0008 /* CXL Sync Header Bypass Enabled */ +#define PCI_CXL_FB_STAT_DRFT_BUF 0x0010 /* Drift Buffer Enabled */ +#define PCI_CXL_FB_STAT_68B_FLIT 0x0020 /* CXL 68B Flit and VH Enabled */ +#define PCI_CXL_FB_STAT_MULT_LOG_DEV 0x0040 /* CXL Multi Logical Device Enabled */ +#define PCI_CXL_FB_STAT_256B_FLIT 0x2000 /* CXL Latency Optimized 256B Flit Enabled */ +#define PCI_CXL_FB_STAT_PBR_FLIT 0x4000 /* CXL PBR Flit Enabled */ +#define PCI_CXL_FB_MOD_TS_DATA 0x10 /* CXL Flex Bus Port Received Modified TS Data Phase1 Register */ +#define PCI_CXL_FB_PORT_CAP2 0x14 /* CXL Flex Bus Port Capability2 Register */ +#define PCI_CXL_FB_CAP2_NOP_HINT 0x01 /* NOP Hint Capable */ +#define PCI_CXL_FB_PORT_CTRL2 0x18 /* CXL Flex Bus Port Control2 Register */ +#define PCI_CXL_FB_CTRL2_NOP_HINT 0x01 /* NOP Hint Enable */ +#define PCI_CXL_FB_PORT_STATUS2 0x1c /* CXL Flex Bus Port Status2 Register */ /* Access Control Services */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ @@ -1295,7 +1343,7 @@ #define PCI_L1PM_SUBSTAT_CAP_PM_L11 0x2 /* PCI-PM L1.1 Supported */ #define PCI_L1PM_SUBSTAT_CAP_ASPM_L12 0x4 /* ASPM L1.2 Supported */ #define PCI_L1PM_SUBSTAT_CAP_ASPM_L11 0x8 /* ASPM L1.1 Supported */ -#define PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP 0x16 /* L1 PM Substates supported */ +#define PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP 0x10 /* L1 PM Substates supported */ #define PCI_L1PM_SUBSTAT_CTL1 0x8 /* L1 PM Substate Control 1 */ #define PCI_L1PM_SUBSTAT_CTL1_PM_L12 0x1 /* PCI-PM L1.2 Enable */ #define PCI_L1PM_SUBSTAT_CTL1_PM_L11 0x2 /* PCI-PM L1.1 Enable */