X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=lib%2Fheader.h;h=5fb4101e87aa04623688d068d27e4b0bc10d1246;hb=6aea909aa02024dad4a3ef1ed63a25a09185d740;hp=3b7bd786a5bba6e8fc662e3c1946f094a864bed2;hpb=72b9b690e81e539fc6b92958a1544f5379a6fa9f;p=pciutils.git diff --git a/lib/header.h b/lib/header.h index 3b7bd78..5fb4101 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1,9 +1,7 @@ /* - * $Id: header.h,v 1.6 2000/05/01 21:34:49 mj Exp $ - * * The PCI Library -- PCI Header Structure (extracted from ) * - * Copyright (c) 1997--1999 Martin Mares + * Copyright (c) 1997--2002 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ @@ -80,8 +78,8 @@ #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ -#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) -#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) +#define PCI_BASE_ADDRESS_MEM_MASK (~(pciaddr_t)0x0f) +#define PCI_BASE_ADDRESS_IO_MASK (~(pciaddr_t)0x03) /* bit 1 is reserved if address_space = 1 */ /* Header type 0 (normal devices) */ @@ -90,7 +88,7 @@ #define PCI_SUBSYSTEM_ID 0x2e #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ #define PCI_ROM_ADDRESS_ENABLE 0x01 -#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) +#define PCI_ROM_ADDRESS_MASK (~(pciaddr_t)0x7ff) #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ @@ -185,6 +183,7 @@ #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ +#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ #define PCI_CAP_SIZEOF 4 @@ -220,21 +219,31 @@ #define PCI_AGP_RFU 3 /* Rest of capability flags */ #define PCI_AGP_STATUS 4 /* Status register */ #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ +#define PCI_AGP_STATUS_ISOCH 0x10000 /* Isochronous transactions supported */ +#define PCI_AGP_STATUS_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ +#define PCI_AGP_STATUS_CAL_MASK 0x1c00 /* Calibration cycle timing */ #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ -#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ -#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ -#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ -#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ -#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ +#define PCI_AGP_STATUS_ITA_COH 0x0100 /* In-aperture accesses always coherent */ +#define PCI_AGP_STATUS_GART64 0x0080 /* 64-bit GART entries supported */ +#define PCI_AGP_STATUS_HTRANS 0x0040 /* If 0, core logic can xlate host CPU accesses thru aperture */ +#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing cycles supported */ +#define PCI_AGP_STATUS_FW 0x0010 /* Fast write transfers supported */ +#define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */ +#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */ +#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */ +#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */ #define PCI_AGP_COMMAND 8 /* Control register */ #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ +#define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */ +#define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */ #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ -#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ -#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ -#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ -#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ -#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ +#define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */ +#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */ +#define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */ +#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */ +#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */ +#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */ #define PCI_AGP_SIZEOF 12 /* Slot Identification */ @@ -257,6 +266,56 @@ #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ +/* PCI-X */ +#define PCI_PCIX_COMMAND 2 /* Command register offset */ +#define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */ +#define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ +#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */ +#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070 +#define PCI_PCIX_COMMAND_RESERVED 0xf80 +#define PCI_PCIX_STATUS 4 /* Status register offset */ +#define PCI_PCIX_STATUS_FUNCTION 0x00000007 +#define PCI_PCIX_STATUS_DEVICE 0x000000f8 +#define PCI_PCIX_STATUS_BUS 0x0000ff00 +#define PCI_PCIX_STATUS_64BIT 0x00010000 +#define PCI_PCIX_STATUS_133MHZ 0x00020000 +#define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ +#define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ +#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */ +#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */ +#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000 +#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000 +#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */ +#define PCI_PCIX_STATUS_RESERVED 0xc0000000 +#define PCI_PCIX_SIZEOF 4 + +/* PCI-X Bridges */ +#define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001 +#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002 +#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */ +#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020 +#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0 +#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00 +#define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */ +#define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007 +#define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8 +#define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00 +#define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000 +#define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000 +#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */ +#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */ +#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */ +#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000 +#define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000 +#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */ +#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */ +#define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff +#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000 +#define PCI_PCIX_BRIDGE_SIZEOF 12 + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded