X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;f=lib%2Fheader.h;h=2bace9357f3fea3e817c2f537b70c8f8cc0f6f67;hb=93c1c6bcc9e2b52652b859986354ddd54ef34058;hp=1a04a7802ae7519dc9c5cff3930e55cb34f1a755;hpb=23b1ee0cef6856d540916e05cc80fab99eaefaa0;p=pciutils.git diff --git a/lib/header.h b/lib/header.h index 1a04a78..2bace93 100644 --- a/lib/header.h +++ b/lib/header.h @@ -3,7 +3,9 @@ * * Copyright (c) 1997--2010 Martin Mares * - * Can be freely distributed and used under the terms of the GNU GPL. + * Can be freely distributed and used under the terms of the GNU GPL v2+ + * + * SPDX-License-Identifier: GPL-2.0-or-later */ /* @@ -252,6 +254,7 @@ #define PCI_EXT_CAP_ID_LMR 0x27 /* Lane Margining at Receiver */ #define PCI_EXT_CAP_ID_HIER_ID 0x28 /* Hierarchy ID */ #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ +#define PCI_EXT_CAP_ID_32GT 0x2a /* Physical Layer 32.0 GT/s */ #define PCI_EXT_CAP_ID_DOE 0x2e /* Data Object Exchange */ /*** Definitions of capabilities ***/ @@ -900,9 +903,13 @@ #define PCI_EXP_DEVCTL2_ARI 0x0020 /* ARI Forwarding */ #define PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */ #define PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */ +#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ +#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ #define PCI_EXP_DEVCTL2_LTR 0x0400 /* LTR enabled */ +#define PCI_EXP_DEVCTL2_EPR_REQ 0x0800 /* Emergency Power Reduction Request */ #define PCI_EXP_DEVCTL2_10BIT_TAG_REQ 0x1000 /* 10 Bit Tag Requester enabled */ #define PCI_EXP_DEVCTL2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */ +#define PCI_EXP_DEVCTL2_EE_TLP_BLK 0x8000 /* End-End TLP Prefix Blocking */ #define PCI_EXP_DEVSTA2 0x2a /* Device Status */ #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */ #define PCI_EXP_LNKCAP2_SPEED(x) (((x) >> 1) & 0x7f) @@ -1069,7 +1076,7 @@ #define PCI_DVSEC_ID_CXL 0 /* Designated Vendor-Specific ID for Intel CXL */ /* PCIe CXL Designated Vendor-Specific Capabilities for Devices: Control, Status */ -#define PCI_CXL_DEV_LEN 0x38 /* CXL Device DVSEC Length */ +#define PCI_CXL_DEV_LEN 0x3c /* CXL Device DVSEC Length */ #define PCI_CXL_DEV_CAP 0x0a /* CXL Capability Register */ #define PCI_CXL_DEV_CAP_CACHE 0x0001 /* CXL.cache Protocol Support */ #define PCI_CXL_DEV_CAP_IO 0x0002 /* CXL.io Protocol Support */ @@ -1087,6 +1094,12 @@ #define PCI_CXL_DEV_CTRL_VIRAL 0x4000 /* CXL Viral Handling Enable */ #define PCI_CXL_DEV_STATUS 0x0e /* CXL Status Register */ #define PCI_CXL_DEV_STATUS_VIRAL 0x4000 /* CXL Viral Handling Status */ +#define PCI_CXL_DEV_CTRL2 0x10 /* CXL Control Register 2 */ +#define PCI_CXL_DEV_CTRL2_DISABLE_CACHING 0x0001 +#define PCI_CXL_DEV_CTRL2_INIT_WB_INVAL 0x0002 +#define PCI_CXL_DEV_CTRL2_INIT_CXL_RST 0x0003 +#define PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN 0x0004 +#define PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST 0x0005 #define PCI_CXL_DEV_STATUS2 0x12 #define PCI_CXL_DEV_STATUS_CACHE_INV 0x0001 #define PCI_CXL_DEV_STATUS_RC 0x0002 /* Device Reset Complete */ @@ -1110,6 +1123,13 @@ #define PCI_CXL_DEV_RANGE2_SIZE_LO 0x2c #define PCI_CXL_DEV_RANGE2_BASE_HI 0x30 #define PCI_CXL_DEV_RANGE2_BASE_LO 0x34 +/* From Rev2 */ +#define PCI_CXL_DEV_CAP3 0x38 +#define PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD 0x0001 +#define PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM 0x0002 +#define PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT 0x0003 +#define PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG 0x0004 + /* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Ports */ #define PCI_CXL_PORT_EXT_LEN 0x28 /* CXL Extensions DVSEC for Ports Length */ @@ -1299,9 +1319,10 @@ #define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */ #define PCI_PRI_CTRL_RESET 0x02 /* Reset */ #define PCI_PRI_STATUS 0x06 /* PRI status register */ -#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ -#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ -#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ +#define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */ +#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */ +#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */ +#define PCI_PRI_STATUS_PASID 0x8000 /* PASID required in PRG response */ #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ @@ -1390,7 +1411,7 @@ #define PCI_DOE_STS 0xC /* DOE Status Register */ #define PCI_DOE_STS_BUSY 0x1 /* DOE Busy */ #define PCI_DOE_STS_INT 0x2 /* DOE Interrupt Status */ -#define PCI_DOE_STS_ERROR 0x3 /* DOE Error */ +#define PCI_DOE_STS_ERROR 0x4 /* DOE Error */ #define PCI_DOE_STS_OBJECT_READY 0x80000000 /* Data Object Ready */ /*