X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;ds=sidebyside;f=tests%2Fcap-pcie-1;h=b69184fb8735b8641017b0951527a27dc75a5e73;hb=3444b81f6b0e83eacb391e10b41f9a7b60e66f4e;hp=f82b71d4cee51c443ef54efa34dbace679d691d3;hpb=d190aae7a3c0dc2b64c6c2c1cb3c1f7b3a069ce0;p=pciutils.git

diff --git a/tests/cap-pcie-1 b/tests/cap-pcie-1
index f82b71d..b69184f 100644
--- a/tests/cap-pcie-1
+++ b/tests/cap-pcie-1
@@ -21,11 +21,11 @@
 			MaxPayload 256 bytes, MaxReadReq 128 bytes
 		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
 		LnkCap:	Port #1, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us
-			ClockPM- Suprise+ LLActRep+ BwNot+
+			ClockPM- Surprise+ LLActRep+ BwNot+
 		LnkCtl:	ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
 			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
 		LnkSta:	Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
-		SltCap:	AttnBtn+ PwrCtrl+ MRL+ AttnInd+ PwrInd+ HotPlug- Surpise-
+		SltCap:	AttnBtn+ PwrCtrl+ MRL+ AttnInd+ PwrInd+ HotPlug- Surprise-
 			Slot # 40, PowerLimit 0.000000; Interlock+ NoCompl-
 		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
 			Control: AttnInd Off, PwrInd Off, Power+ Interlock-