X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;ds=sidebyside;f=ls-ecaps.c;h=d8376dab199310cf442c4faf7e88e5d3a49aa897;hb=fe0df5d38149ae4303300eb429dd501a8bd7da3b;hp=87f51b0ab2166ff91a6beee4e5fcc7a57fae33db;hpb=c8b83c6cd0bc84d1c0a8a0db39c24aee018d9a37;p=pciutils.git diff --git a/ls-ecaps.c b/ls-ecaps.c index 87f51b0..d8376da 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -801,9 +801,43 @@ dvsec_cxl_port(struct device *d, int where) printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2); } +static const char *id[] = { + "empty", + "component registers", + "BAR virtualization", + "CXL device registers"}; + +static inline void +dvsec_decode_block(uint32_t lo, uint32_t hi, char which) +{ + u64 base_hi = hi, base_lo; + u8 bir, block_id; + + bir = BITS(lo, 0, 3); + block_id = BITS(lo, 8, 8); + base_lo = BITS(lo, 16, 16); + + if (!block_id) + return; + + printf("\t\tBlock%c\tBIR: bar%d\tID: %s\n", which, bir, id[block_id]); + printf("\t\t\tRegisterOffset: %016" PCI_U64_FMT_X "\n", (base_hi << 32ULL) | base_lo << 16); +} + +static void +dvsec_cxl_register_locator(struct device *d, int where, int len) +{ + int i, j; + + for (i = 0xc, j = 1; i < len; i += 8, j++) { + dvsec_decode_block(get_conf_long(d, where + i), get_conf_long(d, where + i + 4), j + 0x31); + } +} + static void cap_dvsec_cxl(struct device *d, int id, int where) { + u16 len; u8 rev; printf(": CXL\n"); @@ -825,6 +859,28 @@ cap_dvsec_cxl(struct device *d, int id, int where) dvsec_cxl_port(d, where); break; + case 8: + len = BITS(get_conf_word(d, where + 0x6), 4, 12); + if (!config_fetch(d, where, len)) + return; + + dvsec_cxl_register_locator(d, where, len); + break; + case 2: + printf("\t\tNon-CXL Function Map DVSEC\n"); + break; + case 4: + printf("\t\tGPF DVSEC for Port\n"); + break; + case 5: + printf("\t\tGPF DVSEC for Device\n"); + break; + case 7: + printf("\t\tPCIe DVSEC Flex Bus Port\n"); + break; + case 9: + printf("\t\tMLD DVSEC\n"); + break; default: break; }