X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;ds=sidebyside;f=ls-ecaps.c;h=c6f217eb63d6691a36fa07ff61849726aaa21cbe;hb=c4a1aff42255ccac78c036d7f98a371039a0eede;hp=1c696b49a43a74c4c269407071af4038ee81c0e3;hpb=33088c24c6e8f9a55cc13e072f46233cb8796e5e;p=pciutils.git

diff --git a/ls-ecaps.c b/ls-ecaps.c
index 1c696b4..c6f217e 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -1,7 +1,7 @@
 /*
  *	The PCI Utilities -- Show Extended Capabilities
  *
- *	Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
+ *	Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
  *
  *	Can be freely distributed and used under the terms of the GNU GPL.
  */
@@ -11,6 +11,71 @@
 
 #include "lspci.h"
 
+static void
+cap_tph(struct device *d, int where)
+{
+  u32 tph_cap;
+  printf("Transaction Processing Hints\n");
+  if (verbose < 2)
+    return;
+
+  if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
+    return;
+
+  tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
+
+  if (tph_cap & PCI_TPH_INTVEC_SUP)
+    printf("\t\tInterrupt vector mode supported\n");
+  if (tph_cap & PCI_TPH_DEV_SUP)
+    printf("\t\tDevice specific mode supported\n");
+  if (tph_cap & PCI_TPH_EXT_REQ_SUP)
+    printf("\t\tExtended requester support\n");
+
+  switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
+  case PCI_TPH_ST_NONE:
+    printf("\t\tNo steering table available\n");
+    break;
+  case PCI_TPH_ST_CAP:
+    printf("\t\tSteering table in TPH capability structure\n");
+    break;
+  case PCI_TPH_ST_MSIX:
+    printf("\t\tSteering table in MSI-X table\n");
+    break;
+  default:
+    printf("\t\tReserved steering table location\n");
+    break;
+  }
+}
+
+static u32
+cap_ltr_scale(u8 scale)
+{
+  return 1 << (scale * 5);
+}
+
+static void
+cap_ltr(struct device *d, int where)
+{
+  u32 scale;
+  u16 snoop, nosnoop;
+  printf("Latency Tolerance Reporting\n");
+  if (verbose < 2)
+    return;
+
+  if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
+    return;
+
+  snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
+  scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
+  printf("\t\tMax snoop latency: %lldns\n",
+	 ((unsigned long long)snoop & PCI_LTR_VALUE_MASK) * scale);
+
+  nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
+  scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
+  printf("\t\tMax no snoop latency: %lldns\n",
+	 ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale);
+}
+
 static void
 cap_dsn(struct device *d, int where)
 {
@@ -221,9 +286,10 @@ cap_vc(struct device *d, int where)
   int evc_cnt;
   int arb_table_pos;
   int i, j;
-  static const char ref_clocks[4][6] = { "100ns", "?1", "?2", "?3" };
-  static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "?4", "?5", "?6", "?7" };
-  static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "?6", "?7" };
+  static const char ref_clocks[][6] = { "100ns" };
+  static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
+  static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
+  char buf[8];
 
   printf("Virtual Channel\n");
   if (verbose < 2)
@@ -237,24 +303,26 @@ cap_vc(struct device *d, int where)
   ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
   status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
 
-  evc_cnt = cr1 & 7;
-  printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntrySize=%d\n",
-    (cr1 >> 4) & 7,
-    ref_clocks[(cr1 >> 8) & 3],
-    (cr1 >> 10) & 3);
+  evc_cnt = BITS(cr1, 0, 3);
+  printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
+    BITS(cr1, 4, 3),
+    TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
+    1 << BITS(cr1, 10, 2));
 
-  printf("\t\tArb:\t");
+  printf("\t\tArb:");
   for (i=0; i<8; i++)
     if (arb_selects[i][0] != '?' || cr2 & (1 << i))
-      printf("%s%c ", arb_selects[i], FLAG(cr2, 1 << i));
-  arb_table_pos = (cr2 >> 24) & 0xff;
-  printf("TableOffset=%x\n", arb_table_pos);
+      printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
+  arb_table_pos = BITS(cr2, 24, 8);
 
-  printf("\t\tCtrl:\tArbSelect=%s\n", arb_selects[(ctrl >> 1) & 7]);
+  printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
   printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
 
   if (arb_table_pos)
-    printf("\t\tPort Arbitration Table <?>\n");
+    {
+      arb_table_pos = where + 16*arb_table_pos;
+      printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
+    }
 
   for (i=0; i<=evc_cnt; i++)
     {
@@ -263,20 +331,20 @@ cap_vc(struct device *d, int where)
       u16 rstatus;
       int pat_pos;
 
+      printf("\t\tVC%d:\t", i);
       if (!config_fetch(d, pos, 12))
 	{
-	  printf("VC%d <unreadable>\n", i);
+	  printf("<unreadable>\n");
 	  continue;
 	}
       rcap = get_conf_long(d, pos);
       rctrl = get_conf_long(d, pos+4);
-      rstatus = get_conf_word(d, pos+8);
+      rstatus = get_conf_word(d, pos+10);
 
-      pat_pos = (rcap >> 24) & 0xff;
-      printf("\t\tVC%d:\tCaps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
-	i,
+      pat_pos = BITS(rcap, 24, 8);
+      printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
 	pat_pos,
-	((rcap >> 16) & 0x3f) + 1,
+	BITS(rcap, 16, 6) + 1,
 	FLAG(rcap, 1 << 15));
 
       printf("\t\t\tArb:");
@@ -286,9 +354,9 @@ cap_vc(struct device *d, int where)
 
       printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
 	FLAG(rctrl, 1 << 31),
-	(rctrl >> 24) & 7,
-	vc_arb_selects[(rctrl >> 17) & 7],
-	rctrl & 0xff);
+	BITS(rctrl, 24, 3),
+	TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
+	BITS(rctrl, 0, 8));
 
       printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
 	FLAG(rstatus, 2),
@@ -299,6 +367,139 @@ cap_vc(struct device *d, int where)
     }
 }
 
+static void
+cap_rclink(struct device *d, int where)
+{
+  u32 esd;
+  int num_links;
+  int i;
+  static const char elt_types[][9] = { "Config", "Egress", "Internal" };
+  char buf[8];
+
+  printf("Root Complex Link\n");
+  if (verbose < 2)
+    return;
+
+  if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
+    return;
+
+  esd = get_conf_long(d, where + PCI_RCLINK_ESD);
+  num_links = BITS(esd, 8, 8);
+  printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
+    BITS(esd, 24, 8),
+    BITS(esd, 16, 8),
+    TABLE(elt_types, BITS(esd, 0, 8), buf));
+
+  for (i=0; i<num_links; i++)
+    {
+      int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
+      u32 desc;
+      u32 addr_lo, addr_hi;
+
+      printf("\t\tLink%d:\t", i);
+      if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
+	{
+	  printf("<unreadable>\n");
+	  return;
+	}
+      desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
+      addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
+      addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
+
+      printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
+	BITS(desc, 24, 8),
+	BITS(desc, 16, 8),
+	FLAG(desc, 4),
+	((desc & 2) ? "Config" : "MemMapped"),
+	FLAG(desc, 1));
+
+      if (desc & 2)
+	{
+	  int n = addr_lo & 7;
+	  if (!n)
+	    n = 8;
+	  printf("\t\t\tAddr:\t%02x:%02x.%d  CfgSpace=%08x%08x\n",
+	    BITS(addr_lo, 20, n),
+	    BITS(addr_lo, 15, 5),
+	    BITS(addr_lo, 12, 3),
+	    addr_hi, addr_lo);
+	}
+      else
+	printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
+    }
+}
+
+static void
+cap_evendor(struct device *d, int where)
+{
+  u32 hdr;
+
+  printf("Vendor Specific Information: ");
+  if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
+    {
+      printf("<unreadable>\n");
+      return;
+    }
+
+  hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
+  printf("ID=%04x Rev=%d Len=%03x <?>\n",
+    BITS(hdr, 0, 16),
+    BITS(hdr, 16, 4),
+    BITS(hdr, 20, 12));
+}
+
+static void
+cap_l1pm(struct device *d, int where)
+{
+  u32 l1_cap;
+  int power_on_scale;
+
+  printf("L1 PM Substates\n");
+
+  if (verbose < 2)
+    return;
+
+  if (!config_fetch(d, where + 4, 4))
+    {
+      printf("\t\t<unreadable>\n");
+      return;
+    }
+
+  l1_cap = get_conf_long(d, where + 4);
+  printf("\t\tL1SubCap: ");
+  printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
+    FLAG(l1_cap, 1),
+    FLAG(l1_cap, 2),
+    FLAG(l1_cap, 4),
+    FLAG(l1_cap, 8),
+    FLAG(l1_cap, 16));
+
+  if (BITS(l1_cap, 0, 1) || BITS(l1_cap, 2, 1))
+    {
+      printf("\t\t\t  PortCommonModeRestoreTime=%dus ",
+	BITS(l1_cap, 8,8));
+
+      power_on_scale = BITS(l1_cap, 16, 2);
+
+      printf("PortTPowerOnTime=");
+      switch (power_on_scale)
+	{
+	  case 0:
+	    printf("%dus\n", BITS(l1_cap, 19, 5) * 2);
+	    break;
+	  case 1:
+	    printf("%dus\n", BITS(l1_cap, 19, 5) * 10);
+	    break;
+	  case 2:
+	    printf("%dus\n", BITS(l1_cap, 19, 5) * 100);
+	    break;
+	  default:
+	    printf("<error>\n");
+	    break;
+	}
+    }
+}
+
 void
 show_ext_caps(struct device *d)
 {
@@ -342,7 +543,7 @@ show_ext_caps(struct device *d)
 	    printf("Power Budgeting <?>\n");
 	    break;
 	  case PCI_EXT_CAP_ID_RCLINK:
-	    printf("Root Complex Link <?>\n");
+	    cap_rclink(d, where);
 	    break;
 	  case PCI_EXT_CAP_ID_RCILINK:
 	    printf("Root Complex Internal Link <?>\n");
@@ -357,7 +558,7 @@ show_ext_caps(struct device *d)
 	    printf("Root Bridge Control Block <?>\n");
 	    break;
 	  case PCI_EXT_CAP_ID_VNDR:
-	    printf("Vendor Specific Information <?>\n");
+	    cap_evendor(d, where);
 	    break;
 	  case PCI_EXT_CAP_ID_ACS:
 	    cap_acs(d, where);
@@ -371,6 +572,15 @@ show_ext_caps(struct device *d)
 	  case PCI_EXT_CAP_ID_SRIOV:
 	    cap_sriov(d, where);
 	    break;
+	  case PCI_EXT_CAP_ID_TPH:
+	    cap_tph(d, where);
+	    break;
+	  case PCI_EXT_CAP_ID_LTR:
+	    cap_ltr(d, where);
+	    break;
+	  case PCI_EXT_CAP_ID_L1PM:
+	    cap_l1pm(d, where);
+	    break;
 	  default:
 	    printf("#%02x\n", id);
 	    break;