X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;ds=sidebyside;f=ls-ecaps.c;h=b4e6a630ee05e2eb71f9b62986bd27ad9f2b1cbc;hb=4582426202ad6ac6539305dae2c0b70016f014f4;hp=d8376dab199310cf442c4faf7e88e5d3a49aa897;hpb=fe0df5d38149ae4303300eb429dd501a8bd7da3b;p=pciutils.git diff --git a/ls-ecaps.c b/ls-ecaps.c index d8376da..b4e6a63 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -1,7 +1,7 @@ /* * The PCI Utilities -- Show Extended Capabilities * - * Copyright (c) 1997--2020 Martin Mares + * Copyright (c) 1997--2022 Martin Mares * * Can be freely distributed and used under the terms of the GNU GPL. */ @@ -549,7 +549,7 @@ cap_vc(struct device *d, int where) pat_pos = BITS(rcap, 24, 8); printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n", pat_pos, - BITS(rcap, 16, 6) + 1, + BITS(rcap, 16, 7) + 1, FLAG(rcap, 1 << 15)); printf("\t\t\tArb:"); @@ -710,12 +710,15 @@ cxl_range(u64 base, u64 size, int n) } static void -dvsec_cxl_device(struct device *d, int where, int rev) +dvsec_cxl_device(struct device *d, int rev, int where, int len) { - u32 cache_size, cache_unit_size, l; + u32 cache_size, cache_unit_size; u64 range_base, range_size; u16 w; + if (len < PCI_CXL_DEV_LEN) + return; + /* Legacy 1.1 revs aren't handled */ if (rev < 1) return; @@ -757,33 +760,28 @@ dvsec_cxl_device(struct device *d, int where, int rev) break; } - l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI); - range_size = (u64) l << 32; - l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO); - range_size |= l; - l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI); - range_base = (u64) l << 32; - l = get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO); - range_base |= l; + range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32; + range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO); + range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32; + range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO); cxl_range(range_base, range_size, 1); - l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI); - range_size = (u64) l << 32; - l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO); - range_size |= l; - l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI); - range_base = (u64) l << 32; - l = get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO); - range_base |= l; + range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32; + range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO); + range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32; + range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO); cxl_range(range_base, range_size, 2); } static void -dvsec_cxl_port(struct device *d, int where) +dvsec_cxl_port(struct device *d, int where, int len) { u16 w, m1, m2; u8 b1, b2; + if (len < PCI_CXL_PORT_EXT_LEN) + return; + w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS); printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS)); @@ -801,89 +799,272 @@ dvsec_cxl_port(struct device *d, int where) printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2); } -static const char *id[] = { - "empty", - "component registers", - "BAR virtualization", - "CXL device registers"}; +static void +dvsec_cxl_register_locator(struct device *d, int where, int len) +{ + static const char * const id_names[] = { + "empty", + "component registers", + "BAR virtualization", + "CXL device registers", + "CPMU registers", + }; + + for (int i=0; ; i++) + { + int pos = where + PCI_CXL_RL_BLOCK1_LO + 8*i; + if (pos + 7 >= where + len) + break; + + u32 lo = get_conf_long(d, pos); + u32 hi = get_conf_long(d, pos + 4); + + unsigned int bir = BITS(lo, 0, 3); + unsigned int block_id = BITS(lo, 8, 8); + u64 base = (BITS(lo, 16, 16) << 16) | ((u64) hi << 32); -static inline void -dvsec_decode_block(uint32_t lo, uint32_t hi, char which) + if (!block_id) + continue; + + const char *id_name; + if (block_id < sizeof(id_names) / sizeof(*id_names)) + id_name = id_names[block_id]; + else if (block_id == 0xff) + id_name = "vendor-specific"; + else + id_name = ""; + + printf("\t\tBlock%d: BIR: bar%d, ID: %s, offset: %016" PCI_U64_FMT_X "\n", i + 1, bir, id_name, base); + } +} + +static void +dvsec_cxl_gpf_device(struct device *d, int where) { - u64 base_hi = hi, base_lo; - u8 bir, block_id; + u32 l; + u16 w, duration; + u8 time_base, time_scale; - bir = BITS(lo, 0, 3); - block_id = BITS(lo, 8, 8); - base_lo = BITS(lo, 16, 16); + w = get_conf_word(d, where + PCI_CXL_GPF_DEV_PHASE2_DUR); + time_base = BITS(w, 0, 4); + time_scale = BITS(w, 8, 4); - if (!block_id) - return; + switch (time_scale) + { + case PCI_CXL_GPF_DEV_100US: + case PCI_CXL_GPF_DEV_100MS: + duration = time_base * 100; + break; + case PCI_CXL_GPF_DEV_10US: + case PCI_CXL_GPF_DEV_10MS: + case PCI_CXL_GPF_DEV_10S: + duration = time_base * 10; + break; + case PCI_CXL_GPF_DEV_1US: + case PCI_CXL_GPF_DEV_1MS: + case PCI_CXL_GPF_DEV_1S: + duration = time_base; + break; + default: + /* Reserved */ + printf("\t\tReserved time scale encoding %x\n", time_scale); + duration = time_base; + } - printf("\t\tBlock%c\tBIR: bar%d\tID: %s\n", which, bir, id[block_id]); - printf("\t\t\tRegisterOffset: %016" PCI_U64_FMT_X "\n", (base_hi << 32ULL) | base_lo << 16); + printf("\t\tGPF Phase 2 Duration: %u%s\n", duration, + (time_scale < PCI_CXL_GPF_DEV_1MS) ? "us": + (time_scale < PCI_CXL_GPF_DEV_1S) ? "ms" : + (time_scale == PCI_CXL_GPF_DEV_1S) ? "s" : ""); + + l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW); + printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l); } static void -dvsec_cxl_register_locator(struct device *d, int where, int len) +dvsec_cxl_gpf_port(struct device *d, int where) { - int i, j; + u16 w, timeout; + u8 time_base, time_scale; + + w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE1_CTRL); + time_base = BITS(w, 0, 4); + time_scale = BITS(w, 8, 4); + + switch (time_scale) + { + case PCI_CXL_GPF_PORT_100US: + case PCI_CXL_GPF_PORT_100MS: + timeout = time_base * 100; + break; + case PCI_CXL_GPF_PORT_10US: + case PCI_CXL_GPF_PORT_10MS: + case PCI_CXL_GPF_PORT_10S: + timeout = time_base * 10; + break; + case PCI_CXL_GPF_PORT_1US: + case PCI_CXL_GPF_PORT_1MS: + case PCI_CXL_GPF_PORT_1S: + timeout = time_base; + break; + default: + /* Reserved */ + printf("\t\tReserved time scale encoding %x\n", time_scale); + timeout = time_base; + } + + printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout, + (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us": + (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" : + (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : ""); + + w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL); + time_base = BITS(w, 0, 4); + time_scale = BITS(w, 8, 4); + + switch (time_scale) + { + case PCI_CXL_GPF_PORT_100US: + case PCI_CXL_GPF_PORT_100MS: + timeout = time_base * 100; + break; + case PCI_CXL_GPF_PORT_10US: + case PCI_CXL_GPF_PORT_10MS: + case PCI_CXL_GPF_PORT_10S: + timeout = time_base * 10; + break; + case PCI_CXL_GPF_PORT_1US: + case PCI_CXL_GPF_PORT_1MS: + case PCI_CXL_GPF_PORT_1S: + timeout = time_base; + break; + default: + /* Reserved */ + printf("\t\tReserved time scale encoding %x\n", time_scale); + timeout = time_base; + } + + printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout, + (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us": + (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" : + (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : ""); +} + +static void +dvsec_cxl_flex_bus(struct device *d, int where, int rev) +{ + u16 w; + u32 l, data; - for (i = 0xc, j = 1; i < len; i += 8, j++) { - dvsec_decode_block(get_conf_long(d, where + i), get_conf_long(d, where + i + 4), j + 0x31); + if (rev < 1) + { + printf("\t\tRevision %d not supported\n", rev); + return; } + + w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP); + printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c", + FLAG(w, PCI_CXL_FB_CAP_CACHE), FLAG(w, PCI_CXL_FB_CAP_IO), + FLAG(w, PCI_CXL_FB_CAP_MEM), FLAG(w, PCI_CXL_FB_CAP_68B_FLIT), + FLAG(w, PCI_CXL_FB_CAP_MULT_LOG_DEV)); + + if (rev > 1) + printf(" 256BFlit%c PBRFlit%c", + FLAG(w, PCI_CXL_FB_CAP_256B_FLIT), FLAG(w, PCI_CXL_FB_CAP_PBR_FLIT)); + + w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL); + printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c", + FLAG(w, PCI_CXL_FB_CTRL_CACHE), FLAG(w, PCI_CXL_FB_CTRL_IO), + FLAG(w, PCI_CXL_FB_CTRL_MEM), FLAG(w, PCI_CXL_FB_CTRL_SYNC_HDR_BYP), + FLAG(w, PCI_CXL_FB_CTRL_DRFT_BUF), FLAG(w, PCI_CXL_FB_CTRL_68B_FLIT), + FLAG(w, PCI_CXL_FB_CTRL_MULT_LOG_DEV), FLAG(w, PCI_CXL_FB_CTRL_RCD), + FLAG(w, PCI_CXL_FB_CTRL_RETIMER1), FLAG(w, PCI_CXL_FB_CTRL_RETIMER2)); + + if (rev > 1) + printf(" 256BFlit%c PBRFlit%c", + FLAG(w, PCI_CXL_FB_CTRL_256B_FLIT), FLAG(w, PCI_CXL_FB_CTRL_PBR_FLIT)); + + w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS); + printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c", + FLAG(w, PCI_CXL_FB_STAT_CACHE), FLAG(w, PCI_CXL_FB_STAT_IO), + FLAG(w, PCI_CXL_FB_STAT_MEM), FLAG(w, PCI_CXL_FB_STAT_SYNC_HDR_BYP), + FLAG(w, PCI_CXL_FB_STAT_DRFT_BUF), FLAG(w, PCI_CXL_FB_STAT_68B_FLIT), + FLAG(w, PCI_CXL_FB_STAT_MULT_LOG_DEV)); + + if (rev > 1) + printf(" 256BFlit%c PBRFlit%c", + FLAG(w, PCI_CXL_FB_STAT_256B_FLIT), FLAG(w, PCI_CXL_FB_STAT_PBR_FLIT)); + + l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA); + data = BITS(l, 0, 24); + printf("\n\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data); + + if (rev > 1) + { + u8 nop; + + l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2); + printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT)); + + l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2); + printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT)); + + l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2); + nop = BITS(l, 0, 2); + printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop); + } } static void -cap_dvsec_cxl(struct device *d, int id, int where) +dvsec_cxl_mld(struct device *d, int where) { - u16 len; - u8 rev; + u16 w; + w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD); + + /* Encodings greater than 16 are reserved */ + if (w && w <= PCI_CXL_MLD_MAX_LD) + printf("\t\tNumLogDevs: %d\n", w); +} + +static void +cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len) +{ printf(": CXL\n"); if (verbose < 2) return; - rev = BITS(get_conf_byte(d, where + 0x6), 0, 4); + if (!config_fetch(d, where, len)) + return; - switch (id) { + switch (id) + { case 0: - if (!config_fetch(d, where, PCI_CXL_DEV_LEN)) - return; - - dvsec_cxl_device(d, where, rev); - break; - case 3: - if (!config_fetch(d, where, PCI_CXL_PORT_EXT_LEN)) - return; - - dvsec_cxl_port(d, where); - break; - case 8: - len = BITS(get_conf_word(d, where + 0x6), 4, 12); - if (!config_fetch(d, where, len)) - return; - - dvsec_cxl_register_locator(d, where, len); + dvsec_cxl_device(d, rev, where, len); break; case 2: printf("\t\tNon-CXL Function Map DVSEC\n"); break; + case 3: + dvsec_cxl_port(d, where, len); + break; case 4: - printf("\t\tGPF DVSEC for Port\n"); + dvsec_cxl_gpf_port(d, where); break; case 5: - printf("\t\tGPF DVSEC for Device\n"); + dvsec_cxl_gpf_device(d, where); break; case 7: - printf("\t\tPCIe DVSEC Flex Bus Port\n"); + dvsec_cxl_flex_bus(d, where, rev); + break; + case 8: + dvsec_cxl_register_locator(d, where, len); break; case 9: - printf("\t\tMLD DVSEC\n"); + dvsec_cxl_mld(d, where); break; default: - break; - } + printf("\t\tUnknown ID %04x\n", id); + } } static void @@ -905,7 +1086,7 @@ cap_dvsec(struct device *d, int where) printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len); if (vendor == PCI_DVSEC_VENDOR_ID_CXL && len >= 16) - cap_dvsec_cxl(d, id, where); + cap_dvsec_cxl(d, id, rev, where, len); else printf(" \n"); }