X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;ds=sidebyside;f=ls-caps.c;h=2c99812c4ed25cdb72c7c71054b53365ec78675c;hb=e5d1d2dbb64cafd33f9b012b7959b61319dcd250;hp=a4bf713cac7b8e1a12e75fcfc88768c5a400ed3e;hpb=a242f574431f6624475acdedcb2b4cbeef385766;p=pciutils.git diff --git a/ls-caps.c b/ls-caps.c index a4bf713..2c99812 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -1,9 +1,11 @@ /* * The PCI Utilities -- Show Capabilities * - * Copyright (c) 1997--2010 Martin Mares + * Copyright (c) 1997--2018 Martin Mares * - * Can be freely distributed and used under the terms of the GNU GPL. + * Can be freely distributed and used under the terms of the GNU GPL v2+. + * + * SPDX-License-Identifier: GPL-2.0-or-later */ #include @@ -25,7 +27,7 @@ cap_pm(struct device *d, int where, int cap) FLAG(cap, PCI_PM_CAP_DSI), FLAG(cap, PCI_PM_CAP_D1), FLAG(cap, PCI_PM_CAP_D2), - pm_aux_current[(cap >> 6) & 7], + pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6], FLAG(cap, PCI_PM_CAP_PME_D0), FLAG(cap, PCI_PM_CAP_PME_D1), FLAG(cap, PCI_PM_CAP_PME_D2), @@ -44,8 +46,8 @@ cap_pm(struct device *d, int where, int cap) b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS); if (b) printf("\t\tBridge: PM%c B3%c\n", - FLAG(t, PCI_PM_BPCC_ENABLE), - FLAG(~t, PCI_PM_PPB_B2_B3)); + FLAG(b, PCI_PM_BPCC_ENABLE), + FLAG(~b, PCI_PM_PPB_B2_B3)); } static void @@ -136,17 +138,17 @@ cap_pcix_nobridge(struct device *d, int where) 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)), max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]); printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n", - ((status >> 8) & 0xff), - ((status >> 3) & 0x1f), + (status & PCI_PCIX_STATUS_BUS) >> 8, + (status & PCI_PCIX_STATUS_DEVICE) >> 3, (status & PCI_PCIX_STATUS_FUNCTION), FLAG(status, PCI_PCIX_STATUS_64BIT), FLAG(status, PCI_PCIX_STATUS_133MHZ), FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED), FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC), ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"), - 1 << (9 + ((status >> 21) & 3U)), - max_outstanding[(status >> 23) & 7U], - 1 << (3 + ((status >> 26) & 7U)), + 1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)), + max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23], + 1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)), FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS), FLAG(status, PCI_PCIX_STATUS_266MHZ), FLAG(status, PCI_PCIX_STATUS_533MHZ)); @@ -175,11 +177,11 @@ cap_pcix_bridge(struct device *d, int where) FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC), FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN), FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED), - sec_clock_freq[(secstatus >> 6) & 7]); + sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]); status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS); printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n", - ((status >> 8) & 0xff), - ((status >> 3) & 0x1f), + (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8, + (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3, (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION), FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT), FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ), @@ -231,7 +233,6 @@ cap_ht_pri(struct device *d, int where, int cmd) { u16 lctr0, lcnf0, lctr1, lcnf1, eh; u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn; - char *fmt; printf("HyperTransport: Slave or Primary Interface\n"); if (verbose < 2) @@ -243,22 +244,17 @@ cap_ht_pri(struct device *d, int where, int cmd) if (rid < 0x22 && rid > 0x11) printf("\t\t!!! Possibly incomplete decoding\n"); - if (rid >= 0x22) - fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n"; - else - fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n"; - printf(fmt, + printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c", (cmd & PCI_HT_PRI_CMD_BUID), (cmd & PCI_HT_PRI_CMD_UC) >> 5, FLAG(cmd, PCI_HT_PRI_CMD_MH), - FLAG(cmd, PCI_HT_PRI_CMD_DD), - FLAG(cmd, PCI_HT_PRI_CMD_DUL)); - lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0); + FLAG(cmd, PCI_HT_PRI_CMD_DD)); if (rid >= 0x22) - fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c > 8, - FLAG(lctr0, PCI_HT_LCTR_ISOCEN), - FLAG(lctr0, PCI_HT_LCTR_LSEN), - FLAG(lctr0, PCI_HT_LCTR_EXTCTL), - FLAG(lctr0, PCI_HT_LCTR_64B)); - lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0); + (lctr0 & PCI_HT_LCTR_CRCERR) >> 8); if (rid >= 0x22) - fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n"; + printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c", + FLAG(lctr0, PCI_HT_LCTR_ISOCEN), + FLAG(lctr0, PCI_HT_LCTR_LSEN), + FLAG(lctr0, PCI_HT_LCTR_EXTCTL), + FLAG(lctr0, PCI_HT_LCTR_64B)); + printf("\n"); + + lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0); + if (rid < 0x22) + printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n", + ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI), + ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4), + ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8), + ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12)); else - fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n"; - printf(fmt, - ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI), - ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4), - ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8), - ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12), - FLAG(lcnf0, PCI_HT_LCNF_DFI), - FLAG(lcnf0, PCI_HT_LCNF_DFO), - FLAG(lcnf0, PCI_HT_LCNF_DFIE), - FLAG(lcnf0, PCI_HT_LCNF_DFOE)); + printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n", + ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI), + FLAG(lcnf0, PCI_HT_LCNF_DFI), + ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4), + FLAG(lcnf0, PCI_HT_LCNF_DFO), + ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8), + FLAG(lcnf0, PCI_HT_LCNF_DFIE), + ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12), + FLAG(lcnf0, PCI_HT_LCNF_DFOE)); + lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1); - if (rid >= 0x22) - fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c > 8, + (lctr1 & PCI_HT_LCTR_CRCERR) >> 8); + if (rid >= 0x22) + printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c", FLAG(lctr1, PCI_HT_LCTR_ISOCEN), FLAG(lctr1, PCI_HT_LCTR_LSEN), FLAG(lctr1, PCI_HT_LCTR_EXTCTL), FLAG(lctr1, PCI_HT_LCTR_64B)); + printf("\n"); + lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1); - if (rid >= 0x22) - fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n"; + if (rid < 0x22) + printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n", + ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI), + ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4), + ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8), + ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12)); else - fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n"; - printf(fmt, - ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI), - ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4), - ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8), - ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12), - FLAG(lcnf1, PCI_HT_LCNF_DFI), - FLAG(lcnf1, PCI_HT_LCNF_DFO), - FLAG(lcnf1, PCI_HT_LCNF_DFIE), - FLAG(lcnf1, PCI_HT_LCNF_DFOE)); + printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n", + ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI), + FLAG(lcnf1, PCI_HT_LCNF_DFI), + ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4), + FLAG(lcnf1, PCI_HT_LCNF_DFO), + ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8), + FLAG(lcnf1, PCI_HT_LCNF_DFIE), + ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12), + FLAG(lcnf1, PCI_HT_LCNF_DFOE)); + printf("\t\tRevision ID: %u.%02u\n", (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN)); if (rid < 0x22) return; + lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0); printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ)); printf("\t\tLink Error 0: 600W"); + return; + } + + if (scale == 0 && value >= 0xF0 && value <= 0xFE) + value = 250 + 25 * (value - 0xF0); + + printf("%gW", value * scales[scale]); } static const char *latency_l0s(int value) @@ -659,28 +692,35 @@ static void cap_express_dev(struct device *d, int where, int type) u16 w; t = get_conf_long(d, where + PCI_EXP_DEVCAP); - printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n", + printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d", 128 << (t & PCI_EXP_DEVCAP_PAYLOAD), - (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1, + (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1); + if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) + printf(", Latency L0s %s, L1 %s", latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6), latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9)); + printf("\n"); printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG)); if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE)) printf(" AttnBtn%c AttnInd%c PwrInd%c", FLAG(t, PCI_EXP_DEVCAP_ATN_BUT), FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND)); - printf(" RBE%c FLReset%c", - FLAG(t, PCI_EXP_DEVCAP_RBE), + printf(" RBE%c", + FLAG(t, PCI_EXP_DEVCAP_RBE)); + if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) + printf(" FLReset%c", FLAG(t, PCI_EXP_DEVCAP_FLRESET)); - if (type == PCI_EXP_TYPE_UPSTREAM) - printf("SlotPowerLimit %.3fW", - power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, - (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26)); + if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) || + (type == PCI_EXP_TYPE_PCI_BRIDGE)) + { + printf(" SlotPowerLimit "); + show_power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26); + } printf("\n"); w = get_conf_word(d, where + PCI_EXP_DEVCTL); - printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n", + printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n", FLAG(w, PCI_EXP_DEVCTL_CERE), FLAG(w, PCI_EXP_DEVCTL_NFERE), FLAG(w, PCI_EXP_DEVCTL_FERE), @@ -691,16 +731,17 @@ static void cap_express_dev(struct device *d, int where, int type) FLAG(w, PCI_EXP_DEVCTL_PHANTOM), FLAG(w, PCI_EXP_DEVCTL_AUX_PME), FLAG(w, PCI_EXP_DEVCTL_NOSNOOP)); - if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE) + if (type == PCI_EXP_TYPE_PCI_BRIDGE) printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE)); - if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET)) + if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) && + (t & PCI_EXP_DEVCAP_FLRESET)) printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET)); printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n", 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5), 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12)); w = get_conf_word(d, where + PCI_EXP_DEVSTA); - printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n", + printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n", FLAG(w, PCI_EXP_DEVSTA_CED), FLAG(w, PCI_EXP_DEVSTA_NFED), FLAG(w, PCI_EXP_DEVSTA_FED), @@ -717,17 +758,41 @@ static char *link_speed(int speed) return "2.5GT/s"; case 2: return "5GT/s"; + case 3: + return "8GT/s"; + case 4: + return "16GT/s"; + case 5: + return "32GT/s"; + case 6: + return "64GT/s"; default: return "unknown"; } } +static char *link_compare(int type, int sta, int cap) +{ + if (sta > cap) + return " (overdriven)"; + if (sta == cap) + return ""; + if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_DOWNSTREAM) || + (type == PCI_EXP_TYPE_PCIE_BRIDGE)) + return ""; + return " (downgraded)"; +} + static char *aspm_support(int code) { switch (code) { + case 0: + return "not supported"; case 1: return "L0s"; + case 2: + return "L1"; case 3: return "L0s L1"; default: @@ -743,30 +808,41 @@ static const char *aspm_enabled(int code) static void cap_express_link(struct device *d, int where, int type) { - u32 t; + u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width; u16 w; t = get_conf_long(d, where + PCI_EXP_LNKCAP); - printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n", + aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10; + cap_speed = t & PCI_EXP_LNKCAP_SPEED; + cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4; + printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s", t >> 24, - link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4, - aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10), - latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12), - latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15)); - printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c\n", + link_speed(cap_speed), cap_width, + aspm_support(aspm)); + if (aspm) + { + printf(", Exit Latency "); + if (aspm & 1) + printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12)); + if (aspm & 2) + printf("%sL1 %s", (aspm & 1) ? ", " : "", + latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15)); + } + printf("\n"); + printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n", FLAG(t, PCI_EXP_LNKCAP_CLOCKPM), FLAG(t, PCI_EXP_LNKCAP_SURPRISE), FLAG(t, PCI_EXP_LNKCAP_DLLA), - FLAG(t, PCI_EXP_LNKCAP_LBNC)); + FLAG(t, PCI_EXP_LNKCAP_LBNC), + FLAG(t, PCI_EXP_LNKCAP_AOC)); w = get_conf_word(d, where + PCI_EXP_LNKCTL); printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM)); if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) || - (type == PCI_EXP_TYPE_LEG_END)) - printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64); - printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n", + (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE)) + printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64); + printf(" LnkDisable%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n", FLAG(w, PCI_EXP_LNKCTL_DISABLE), - FLAG(w, PCI_EXP_LNKCTL_RETRAIN), FLAG(w, PCI_EXP_LNKCTL_CLOCK), FLAG(w, PCI_EXP_LNKCTL_XSYNCH), FLAG(w, PCI_EXP_LNKCTL_CLOCKPM), @@ -775,9 +851,14 @@ static void cap_express_link(struct device *d, int where, int type) FLAG(w, PCI_EXP_LNKCTL_AUTBWIE)); w = get_conf_word(d, where + PCI_EXP_LNKSTA); - printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n", - link_speed(w & PCI_EXP_LNKSTA_SPEED), - (w & PCI_EXP_LNKSTA_WIDTH) >> 4, + sta_speed = w & PCI_EXP_LNKSTA_SPEED; + sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4; + printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n", + link_speed(sta_speed), + link_compare(type, sta_speed, cap_speed), + sta_width, + link_compare(type, sta_width, cap_width)); + printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n", FLAG(w, PCI_EXP_LNKSTA_TR_ERR), FLAG(w, PCI_EXP_LNKSTA_TRAIN), FLAG(w, PCI_EXP_LNKSTA_SL_CLK), @@ -806,9 +887,10 @@ static void cap_express_slot(struct device *d, int where) FLAG(t, PCI_EXP_SLTCAP_PWRI), FLAG(t, PCI_EXP_SLTCAP_HPC), FLAG(t, PCI_EXP_SLTCAP_HPS)); - printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n", - t >> 19, - power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15), + printf("\t\t\tSlot #%d, PowerLimit ", + (t & PCI_EXP_SLTCAP_PSN) >> 19); + show_power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15); + printf("; Interlock%c NoCompl%c\n", FLAG(t, PCI_EXP_SLTCAP_INTERLOCK), FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP)); @@ -843,7 +925,13 @@ static void cap_express_slot(struct device *d, int where) static void cap_express_root(struct device *d, int where) { - u32 w = get_conf_word(d, where + PCI_EXP_RTCTL); + u32 w; + + w = get_conf_word(d, where + PCI_EXP_RTCAP); + printf("\t\tRootCap: CRSVisible%c\n", + FLAG(w, PCI_EXP_RTCAP_CRSVIS)); + + w = get_conf_word(d, where + PCI_EXP_RTCTL); printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n", FLAG(w, PCI_EXP_RTCTL_SECEE), FLAG(w, PCI_EXP_RTCTL_SENFEE), @@ -851,11 +939,7 @@ static void cap_express_root(struct device *d, int where) FLAG(w, PCI_EXP_RTCTL_PMEIE), FLAG(w, PCI_EXP_RTCTL_CRSVIS)); - w = get_conf_word(d, where + PCI_EXP_RTCAP); - printf("\t\tRootCap: CRSVisible%c\n", - FLAG(w, PCI_EXP_RTCAP_CRSVIS)); - - w = get_conf_word(d, where + PCI_EXP_RTSTA); + w = get_conf_long(d, where + PCI_EXP_RTSTA); printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n", w & PCI_EXP_RTSTA_PME_REQID, FLAG(w, PCI_EXP_RTSTA_PME_STATUS), @@ -916,28 +1000,213 @@ static const char *cap_express_dev2_timeout_value(int type) } } +static const char *cap_express_devcap2_obff(int obff) +{ + switch (obff) + { + case 1: + return "Via message"; + case 2: + return "Via WAKE#"; + case 3: + return "Via message/WAKE#"; + default: + return "Not Supported"; + } +} + +static const char *cap_express_devcap2_epr(int epr) +{ + switch (epr) + { + case 1: + return "Dev Specific"; + case 2: + return "Form Factor Dev Specific"; + case 3: + return "Reserved"; + default: + return "Not Supported"; + } +} + +static const char *cap_express_devcap2_lncls(int lncls) +{ + switch (lncls) + { + case 1: + return "64byte cachelines"; + case 2: + return "128byte cachelines"; + case 3: + return "Reserved"; + default: + return "Not Supported"; + } +} + +static const char *cap_express_devcap2_tphcomp(int tph) +{ + switch (tph) + { + case 1: + return "TPHComp+ ExtTPHComp-"; + case 2: + /* Reserved; intentionally left blank */ + return ""; + case 3: + return "TPHComp+ ExtTPHComp+"; + default: + return "TPHComp- ExtTPHComp-"; + } +} + +static const char *cap_express_devctl2_obff(int obff) +{ + switch (obff) + { + case 0: + return "Disabled"; + case 1: + return "Via message A"; + case 2: + return "Via message B"; + case 3: + return "Via WAKE#"; + default: + return "Unknown"; + } +} + +static int +device_has_memory_space_bar(struct device *d) +{ + struct pci_dev *p = d->dev; + int i, found = 0; + + for (i=0; i<6; i++) + if (p->base_addr[i] || p->size[i]) + { + if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO)) + { + found = 1; + break; + } + } + return found; +} + static void cap_express_dev2(struct device *d, int where, int type) { u32 l; u16 w; + int has_mem_bar = device_has_memory_space_bar(d); l = get_conf_long(d, where + PCI_EXP_DEVCAP2); - printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c", - cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)), - FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS)); + printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c", + cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)), + FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS), + FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP), + FLAG(l, PCI_EXP_DEVCAP2_LTR)); + printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c", + FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP), + FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ), + cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)), + FLAG(l, PCI_EXP_DEVCAP2_EXTFMT), + FLAG(l, PCI_EXP_DEVCAP2_EE_TLP)); + + if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP)) + { + printf(", MaxEETLPPrefixes %d", + PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4); + } + + printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c", + cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)), + FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT)); + printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS)); + + if (type == PCI_EXP_TYPE_ROOT_PORT) + printf(" LN System CLS %s,", + cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l))); + + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT) + printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l))); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM) - printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI)); + printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI)); else printf("\n"); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || + type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar) + { + printf("\t\t\t AtomicOpsCap:"); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || + type == PCI_EXP_TYPE_DOWNSTREAM) + printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING)); + if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar) + printf(" 32bit%c 64bit%c 128bitCAS%c", + FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP), + FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP), + FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP)); + printf("\n"); + } w = get_conf_word(d, where + PCI_EXP_DEVCTL2); printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c", - cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)), - FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS)); + cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)), + FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS)); if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM) - printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI)); + printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI)); else printf("\n"); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || + type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT || + type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END) + { + printf("\t\t\t AtomicOpsCtl:"); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT || + type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END) + printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN)); + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM || + type == PCI_EXP_TYPE_DOWNSTREAM) + printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK)); + printf("\n"); + } + printf("\t\t\t IDOReq%c IDOCompl%c LTR%c EmergencyPowerReductionReq%c\n", + FLAG(w, PCI_EXP_DEVCTL2_IDO_REQ_EN), + FLAG(w, PCI_EXP_DEVCTL2_IDO_CMP_EN), + FLAG(w, PCI_EXP_DEVCTL2_LTR), + FLAG(w, PCI_EXP_DEVCTL2_EPR_REQ)); + printf("\t\t\t 10BitTagReq%c OBFF %s, EETLPPrefixBlk%c\n", + FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ), + cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)), + FLAG(w, PCI_EXP_DEVCTL2_EE_TLP_BLK)); +} + +static const char *cap_express_link2_speed_cap(int vector) +{ + /* + * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not + * permitted to skip support for any data rates between 2.5GT/s and the + * highest supported rate. + */ + if (vector & 0x40) + return "RsvdP"; + if (vector & 0x20) + return "2.5-64GT/s"; + if (vector & 0x10) + return "2.5-32GT/s"; + if (vector & 0x08) + return "2.5-16GT/s"; + if (vector & 0x04) + return "2.5-8GT/s"; + if (vector & 0x02) + return "2.5-5GT/s"; + if (vector & 0x01) + return "2.5GT/s"; + + return "Unknown"; } static const char *cap_express_link2_speed(int type) @@ -949,6 +1218,14 @@ static const char *cap_express_link2_speed(int type) return "2.5GT/s"; case 2: return "5GT/s"; + case 3: + return "8GT/s"; + case 4: + return "16GT/s"; + case 5: + return "32GT/s"; + case 6: + return "64GT/s"; default: return "Unknown"; } @@ -967,6 +1244,35 @@ static const char *cap_express_link2_deemphasis(int type) } } +static const char *cap_express_link2_compliance_preset(int type) +{ + switch (type) + { + case 0: + return "-6dB de-emphasis, 0dB preshoot"; + case 1: + return "-3.5dB de-emphasis, 0dB preshoot"; + case 2: + return "-4.4dB de-emphasis, 0dB preshoot"; + case 3: + return "-2.5dB de-emphasis, 0dB preshoot"; + case 4: + return "0dB de-emphasis, 0dB preshoot"; + case 5: + return "0dB de-emphasis, 1.9dB preshoot"; + case 6: + return "0dB de-emphasis, 2.5dB preshoot"; + case 7: + return "-6.0dB de-emphasis, 3.5dB preshoot"; + case 8: + return "-3.5dB de-emphasis, 3.5dB preshoot"; + case 9: + return "0dB de-emphasis, 3.5dB preshoot"; + default: + return "Unknown"; + } +} + static const char *cap_express_link2_transmargin(int type) { switch (type) @@ -985,26 +1291,97 @@ static const char *cap_express_link2_transmargin(int type) } } -static void cap_express_link2(struct device *d, int where, int type UNUSED) +static const char *cap_express_link2_crosslink_res(int crosslink) { + switch (crosslink) + { + case 0: + return "unsupported"; + case 1: + return "Upstream Port"; + case 2: + return "Downstream Port"; + default: + return "incomplete"; + } +} + +static const char *cap_express_link2_component(int presence) +{ + switch (presence) + { + case 0: + return "Link Down - Not Determined"; + case 1: + return "Link Down - Not Present"; + case 2: + return "Link Down - Present"; + case 4: + return "Link Up - Present"; + case 5: + return "Link Up - Present and DRS Received"; + default: + return "Reserved"; + } +} + +static void cap_express_link2(struct device *d, int where, int type) +{ + u32 l = 0; u16 w; - w = get_conf_word(d, where + PCI_EXP_LNKCTL2); - printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c, Selectable De-emphasis: %s\n" - "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n" - "\t\t\t Compliance De-emphasis: %s\n", + if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) && + (d->dev->dev != 0 || d->dev->func != 0))) { + /* Link Capabilities 2 was reserved before PCIe r3.0 */ + l = get_conf_long(d, where + PCI_EXP_LNKCAP2); + if (l) { + printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c " + "Retimer%c 2Retimers%c DRS%c\n", + cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)), + FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK), + FLAG(l, PCI_EXP_LNKCAP2_RETIMER), + FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS), + FLAG(l, PCI_EXP_LNKCAP2_DRS)); + } + + w = get_conf_word(d, where + PCI_EXP_LNKCTL2); + printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c", cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)), FLAG(w, PCI_EXP_LNKCTL2_CMPLNC), - FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS), - cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)), + FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS)); + if (type == PCI_EXP_TYPE_DOWNSTREAM) + printf(", Selectable De-emphasis: %s", + cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w))); + printf("\n" + "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n" + "\t\t\t Compliance Preset/De-emphasis: %s\n", cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)), FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC), FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS), - cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w))); + cap_express_link2_compliance_preset(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w))); + } w = get_conf_word(d, where + PCI_EXP_LNKSTA2); - printf("\t\tLnkSta2: Current De-emphasis Level: %s\n", - cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w))); + printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n" + "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n" + "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s", + cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)), + FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP), + FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1), + FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2), + FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3), + FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ), + FLAG(w, PCI_EXP_LINKSTA2_RETIMER), + FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS), + cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w))); + + if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) { + printf(", DRS%c\n" + "\t\t\t DownstreamComp: %s\n", + FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD), + cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w))); + } else + printf("\n"); } static void cap_express_slot2(struct device *d UNUSED, int where UNUSED) @@ -1012,12 +1389,13 @@ static void cap_express_slot2(struct device *d UNUSED, int where UNUSED) /* No capabilities that require this field in PCIe rev2.0 spec. */ } -static void +static int cap_express(struct device *d, int where, int cap) { int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4; int size; int slot = 0; + int link = 1; printf("Express "); if (verbose >= 2) @@ -1042,52 +1420,59 @@ cap_express(struct device *d, int where, int cap) printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT)); break; case PCI_EXP_TYPE_PCI_BRIDGE: - printf("PCI/PCI-X Bridge"); + printf("PCI-Express to PCI/PCI-X Bridge"); break; case PCI_EXP_TYPE_PCIE_BRIDGE: - printf("PCI/PCI-X to PCI-Express Bridge"); + slot = cap & PCI_EXP_FLAGS_SLOT; + printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)", + FLAG(cap, PCI_EXP_FLAGS_SLOT)); break; case PCI_EXP_TYPE_ROOT_INT_EP: + link = 0; printf("Root Complex Integrated Endpoint"); break; case PCI_EXP_TYPE_ROOT_EC: + link = 0; printf("Root Complex Event Collector"); break; default: printf("Unknown type %d", type); } - printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9); + printf(", IntMsgNum %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9); if (verbose < 2) - return; + return type; size = 16; if (slot) size = 24; - if (type == PCI_EXP_TYPE_ROOT_PORT) + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) size = 32; if (!config_fetch(d, where + PCI_EXP_DEVCAP, size)) - return; + return type; cap_express_dev(d, where, type); - cap_express_link(d, where, type); + if (link) + cap_express_link(d, where, type); if (slot) cap_express_slot(d, where); - if (type == PCI_EXP_TYPE_ROOT_PORT) + if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) cap_express_root(d, where); if ((cap & PCI_EXP_FLAGS_VERS) < 2) - return; + return type; size = 16; if (slot) size = 24; if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size)) - return; + return type; cap_express_dev2(d, where, type); - cap_express_link2(d, where, type); + if (link) + cap_express_link2(d, where, type); if (slot) cap_express_slot2(d, where); + return type; } static void @@ -1187,15 +1572,169 @@ cap_sata_hba(struct device *d, int where, int cap) printf(" BAR??%d\n", bar); } +static const char *cap_ea_property(int p, int is_secondary) +{ + switch (p) { + case 0x00: + return "memory space, non-prefetchable"; + case 0x01: + return "memory space, prefetchable"; + case 0x02: + return "I/O space"; + case 0x03: + return "VF memory space, prefetchable"; + case 0x04: + return "VF memory space, non-prefetchable"; + case 0x05: + return "allocation behind bridge, non-prefetchable memory"; + case 0x06: + return "allocation behind bridge, prefetchable memory"; + case 0x07: + return "allocation behind bridge, I/O space"; + case 0xfd: + return "memory space resource unavailable for use"; + case 0xfe: + return "I/O space resource unavailable for use"; + case 0xff: + if (is_secondary) + return "entry unavailable for use, PrimaryProperties should be used"; + else + return "entry unavailable for use"; + default: + return NULL; + } +} + +static void cap_ea(struct device *d, int where, int cap) +{ + int entry; + int entry_base = where + 4; + int num_entries = BITS(cap, 0, 6); + u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f; + + printf("Enhanced Allocation (EA): NumEntries=%u", num_entries); + if (htype == PCI_HEADER_TYPE_BRIDGE) { + byte fixed_sub, fixed_sec; + + entry_base += 4; + if (!config_fetch(d, where + 4, 2)) { + printf("\n"); + return; + } + fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY); + fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE); + printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub); + } + printf("\n"); + if (verbose < 2) + return; + + for (entry = 0; entry < num_entries; entry++) { + int max_offset_high_pos, has_base_high, has_max_offset_high; + u32 entry_header; + u32 base, max_offset; + int es, bei, pp, sp; + const char *prop_text; + + if (!config_fetch(d, entry_base, 4)) + return; + entry_header = get_conf_long(d, entry_base); + es = BITS(entry_header, 0, 3); + bei = BITS(entry_header, 4, 4); + pp = BITS(entry_header, 8, 8); + sp = BITS(entry_header, 16, 8); + if (!config_fetch(d, entry_base + 4, es * 4)) + return; + printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry, + FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE), + FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es); + printf("\t\t\t BAR Equivalent Indicator: "); + switch (bei) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + printf("BAR %u", bei); + break; + case 6: + printf("resource behind function"); + break; + case 7: + printf("not indicated"); + break; + case 8: + printf("expansion ROM"); + break; + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + printf("VF-BAR %u", bei - 9); + break; + default: + printf("reserved"); + break; + } + printf("\n"); + + prop_text = cap_ea_property(pp, 0); + printf("\t\t\t PrimaryProperties: "); + if (prop_text) + printf("%s\n", prop_text); + else + printf("[%02x]\n", pp); + + prop_text = cap_ea_property(sp, 1); + printf("\t\t\t SecondaryProperties: "); + if (prop_text) + printf("%s\n", prop_text); + else + printf("[%02x]\n", sp); + + base = get_conf_long(d, entry_base + 4); + has_base_high = ((base & 2) != 0); + base &= ~3; + + max_offset = get_conf_long(d, entry_base + 8); + has_max_offset_high = ((max_offset & 2) != 0); + max_offset |= 3; + max_offset_high_pos = entry_base + 12; + + printf("\t\t\t Base: "); + if (has_base_high) { + u32 base_high = get_conf_long(d, entry_base + 12); + + printf("%x", base_high); + max_offset_high_pos += 4; + } + printf("%08x\n", base); + + printf("\t\t\t MaxOffset: "); + if (has_max_offset_high) { + u32 max_offset_high = get_conf_long(d, max_offset_high_pos); + + printf("%x", max_offset_high); + } + printf("%08x\n", max_offset); + + entry_base += 4 + 4 * es; + } +} + void -show_caps(struct device *d) +show_caps(struct device *d, int where) { int can_have_ext_caps = 0; + int type = -1; if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST) { - int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3; byte been_there[256]; + where = get_conf_byte(d, where) & ~3; memset(been_there, 0, 256); while (where) { @@ -1222,6 +1761,9 @@ show_caps(struct device *d) } switch (id) { + case PCI_CAP_ID_NULL: + printf("Null\n"); + break; case PCI_CAP_ID_PM: cap_pm(d, where, cap); break; @@ -1248,7 +1790,7 @@ show_caps(struct device *d) cap_ht(d, where, cap); break; case PCI_CAP_ID_VNDR: - printf("Vendor Specific Information: Len=%02x \n", BITS(cap, 0, 8)); + show_vendor_caps(d, where, cap); break; case PCI_CAP_ID_DBG: cap_debug_port(cap); @@ -1269,7 +1811,7 @@ show_caps(struct device *d) printf("Secure device \n"); break; case PCI_CAP_ID_EXP: - cap_express(d, where, cap); + type = cap_express(d, where, cap); can_have_ext_caps = 1; break; case PCI_CAP_ID_MSIX: @@ -1281,12 +1823,15 @@ show_caps(struct device *d) case PCI_CAP_ID_AF: cap_af(d, where); break; + case PCI_CAP_ID_EA: + cap_ea(d, where, cap); + break; default: - printf("#%02x [%04x]\n", id, cap); + printf("Capability ID %#02x [%04x]\n", id, cap); } where = next; } } if (can_have_ext_caps) - show_ext_caps(d); + show_ext_caps(d, type); }