X-Git-Url: http://mj.ucw.cz/gitweb/?a=blobdiff_plain;ds=sidebyside;f=lib%2Fpci.h;h=dbdb02fcfd2d719a008596d43789a83cb75757cc;hb=3b35571588efef33489d3bb6e4436dc7581596be;hp=41a162b9a3970bf29178ae2373dbdf4bde94ac2d;hpb=a165591213039657f65a466ba1762e02a1c6e310;p=pciutils.git

diff --git a/lib/pci.h b/lib/pci.h
index 41a162b..dbdb02f 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -1,9 +1,11 @@
 /*
  *	The PCI Library
  *
- *	Copyright (c) 1997--2020 Martin Mares <mj@ucw.cz>
+ *	Copyright (c) 1997--2023 Martin Mares <mj@ucw.cz>
  *
- *	Can be freely distributed and used under the terms of the GNU GPL.
+ *	Can be freely distributed and used under the terms of the GNU GPL v2+
+ *
+ *	SPDX-License-Identifier: GPL-2.0-or-later
  */
 
 #ifndef _PCI_LIB_H
@@ -16,7 +18,7 @@
 #include "header.h"
 #include "types.h"
 
-#define PCI_LIB_VERSION 0x030800
+#define PCI_LIB_VERSION 0x030a00
 
 #ifndef PCI_ABI
 #define PCI_ABI
@@ -44,7 +46,11 @@ enum pci_access_type {
   PCI_ACCESS_SYLIXOS_DEVICE,		/* SylixOS pci */
   PCI_ACCESS_HURD,			/* GNU/Hurd */
   PCI_ACCESS_WIN32_CFGMGR32,		/* Win32 cfgmgr32.dll */
+  PCI_ACCESS_WIN32_KLDBG,		/* Win32 kldbgdrv.sys */
   PCI_ACCESS_WIN32_SYSDBG,		/* Win32 NT SysDbg */
+  PCI_ACCESS_MMIO_TYPE1,		/* MMIO ports, type 1 */
+  PCI_ACCESS_MMIO_TYPE1_EXT,		/* MMIO ports, type 1 extended */
+  PCI_ACCESS_ECAM,			/* PCIe ECAM via /dev/mem */
   PCI_ACCESS_MAX
 };
 
@@ -75,15 +81,16 @@ struct pci_access {
   struct pci_param *params;
   struct id_entry **id_hash;		/* names.c */
   struct id_bucket *current_id_bucket;
-  int id_load_failed;
+  int id_load_attempted;
   int id_cache_status;			/* 0=not read, 1=read, 2=dirty */
+  char *id_cache_name;
   struct udev *id_udev;			/* names-hwdb.c */
   struct udev_hwdb *id_udev_hwdb;
   int fd;				/* proc/sys: fd for config space */
   int fd_rw;				/* proc/sys: fd opened read-write */
-  int fd_pos;				/* proc/sys: current position */
   int fd_vpd;				/* sys: fd for VPD */
   struct pci_dev *cached_dev;		/* proc/sys: device the fds are for */
+  void *backend_data;			/* Private data of the back end */
 };
 
 /* Initialize PCI access */
@@ -158,7 +165,7 @@ struct pci_dev {
   u8 *cache;				/* Cached config registers */
   int cache_len;
   int hdrtype;				/* Cached low 7 bits of header type, -1 if unknown */
-  void *aux;				/* Auxiliary data for use by the back-end */
+  void *backend_data;			/* Private data for of the back end */
   struct pci_property *properties;	/* A linked list of extra properties */
   struct pci_cap *last_cap;		/* Last capability in the list */
 };
@@ -167,14 +174,17 @@ struct pci_dev {
 #define PCI_ADDR_MEM_MASK (~(pciaddr_t) 0xf)
 #define PCI_ADDR_FLAG_MASK 0xf
 
-u8 pci_read_byte(struct pci_dev *, int pos) PCI_ABI; /* Access to configuration space */
+/* Access to configuration space */
+u8 pci_read_byte(struct pci_dev *, int pos) PCI_ABI;
 u16 pci_read_word(struct pci_dev *, int pos) PCI_ABI;
 u32 pci_read_long(struct pci_dev *, int pos) PCI_ABI;
-int pci_read_block(struct pci_dev *, int pos, u8 *buf, int len) PCI_ABI;
 int pci_read_vpd(struct pci_dev *d, int pos, u8 *buf, int len) PCI_ABI;
 int pci_write_byte(struct pci_dev *, int pos, u8 data) PCI_ABI;
 int pci_write_word(struct pci_dev *, int pos, u16 data) PCI_ABI;
 int pci_write_long(struct pci_dev *, int pos, u32 data) PCI_ABI;
+
+/* Configuration space as a sequence of bytes (little-endian) */
+int pci_read_block(struct pci_dev *, int pos, u8 *buf, int len) PCI_ABI;
 int pci_write_block(struct pci_dev *, int pos, u8 *buf, int len) PCI_ABI;
 
 /*